[PATCH] D48223: DAG combine "and|or (select c, -1, 0), x" -> "select c, x, 0|-1"

Roman Lebedev via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Sat Jun 16 02:00:29 PDT 2018


lebedev.ri added inline comments.


================
Comment at: test/CodeGen/X86/dagcombine-select.ll:1
+; RUN: llc -march=x86-64 -verify-machineinstrs < %s | FileCheck -enable-var-scope %s
+
----------------
lebedev.ri wrote:
> Most tests (and practically all new x86 tests) use `utils/update_llc_test_checks.py` script to auto-generate these check lines.
(not actually done, that does not look like the utility's output, and the first line does not say the script was used)


================
Comment at: test/CodeGen/X86/dagcombine-select.ll:3-17
+; CHECK-LABEL: {{^}}select_and1:
+; CHECK:      cmpl    $11, %edi
+; CHECK-NEXT: cmovgel %esi, %eax
+; CHECK-NEXT: retq
+define i32 @select_and1(i32 %x, i32 %y) {
+  %c = icmp slt i32 %x, 11
+  %s = select i1 %c, i32 0, i32 -1
----------------
rampitec wrote:
> rampitec wrote:
> > lebedev.ri wrote:
> > > Hm, is there some omitted instruction, or is this actually better than what we currently normally do?
> > > https://godbolt.org/g/7ULPfH
> > Yes. I have updated the test to contain the full ISA. First xor to zero out eax was omitted.
> > I am not sure what compiler explorer does, but that is what trunk llc has produced:
> > 
> > 
> > ```
> >         xorl    %eax, %eax
> >         cmpl    $11, %edi
> >         setl    %al
> >         decl    %eax
> >         andl    %esi, %eax
> >         retq
> > 
> > ```
> > 
> > I assume difference comes from running or not running opt.
> E.g. compare w/o opt: https://godbolt.org/g/NMZ9he
Ok, so the only difference is that the strictness of the comparison is inverted (`cmovg` vs `cmovge` and the other way around).


https://reviews.llvm.org/D48223





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