[PATCH] D47681: [DAGCombiner] Bug 31275- Extract a shift from a constant mul or udiv if a rotate can be formed

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


================
Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:490
+    /// the rotate pattern. 
+    /// Attempts to fold: 
+    ///   (or (shrl (mul v c0) c1) (mul v c2)) ->
----------------
In other words, the cases where `c0`, `c1`, `c2` were power-of-two, and thus instcombine turned them into shifts.
So additional [straight-forward] cases are:
```
    ///   (or (shrl (shl v c0') c1) (shl v c2')) ->
    ///   (or (shrl (shl v c0') c1) (shl (shl v c0') c3))
    /// and
    ///   (or (shrl v c0') (shl (shrl v c1') c2)) ->
    ///   (or (shrl (shrl v c1') c3) (shl (shrl v c1') c2))
```
There is also an additional problem when we are/will convert shrl+shl / shl+rhrl into masking...


https://reviews.llvm.org/D47681