[PATCH] D48131: [RISCV] Implement codegen for cmpxchg on RV32I

[Alex Bradbury via Phabricator via llvm-commits]

asb created this revision.
asb added reviewers: jyknight, eli.friedman, jfb, theraven.
Herald added subscribers: rogfer01, mgrang, edward-jones, zzheng, shiva0217, kito-cheng, niosHD, sabuasal, apazos, simoncook, johnrusso, rbar.
asb added dependencies: D48130: [AtomicExpandPass]: Add a hook for custom cmpxchg expansion in IR, D48129: [RISCV] Improved lowering for bit-wise atomicrmw {i8,i16} on RV32A.

Utilise a similar lowering strategy to https://reviews.llvm.org/D47882.

All cmpxchg are lowered as 'strong' currently and failure ordering is ignored. I believe this is conservative but correct.


https://reviews.llvm.org/D48131

Files:
  include/llvm/IR/IntrinsicsRISCV.td
  lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
  lib/Target/RISCV/RISCVISelLowering.cpp
  lib/Target/RISCV/RISCVISelLowering.h
  lib/Target/RISCV/RISCVInstrInfoA.td
  test/CodeGen/RISCV/atomic-cmpxchg.ll

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