[PATCH] D47587: [RISCV] Codegen support for atomic operations on RV32I

[Alex Bradbury via Phabricator via llvm-commits]

asb added inline comments.


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Comment at: lib/Target/RISCV/RISCVInstrInfo.td:756
+// fence acq_rel -> fence.tso
+def : Pat<(atomic_fence (i32 6), (imm)), (FENCE_TSO)>;
+// fence seq_cst -> fence rw, rw
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jyknight wrote:
> Did you miss uploading the part of the change to add a definition of FENCE_TSO? I don't see where that's defined here.
> 
> But marking LGTM anyways, assuming that'll get fixed before commit.
I committed MC layer support for fence.tso directly (i.e. with post-commit review). MC layer fence.tso support is logically independent of this patch, and the patch was trivial. See rL334278.


https://reviews.llvm.org/D47587