[PATCH] D48074: [ARM] Enable useAA() for the in-order Cortex-R52

[Dave Green via Phabricator via llvm-commits]

dmgreen created this revision.
dmgreen added reviewers: efriedma, javed.absar, fhahn, hfinkel.
Herald added subscribers: chrib, kristof.beyls.
dmgreen added a comment.

Requires https://reviews.llvm.org/D48029 to survives a bootstrap, but that looks like a more generic error than having to use this option. Otherwise I believe this is safe.


This option allows codegen (such as DAGCombine or MI scheduling) to use alias analysis information, which can help with the codegen on in-order cpu's. Here I have done things the same way as AArch64, adding a subtarget feature to enable this for specific cores.

I was going to enable this for A53 too, but seeing as we happen to not have a AArch32 A53 schedule, the usefulness is not as high as R52.


https://reviews.llvm.org/D48074

Files:
  lib/Target/ARM/ARM.td
  lib/Target/ARM/ARMSubtarget.h
  test/CodeGen/ARM/useaa.ll


Index: test/CodeGen/ARM/useaa.ll
===================================================================
--- /dev/null
+++ test/CodeGen/ARM/useaa.ll
@@ -0,0 +1,26 @@
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-r52 | FileCheck %s --check-prefix=CHECK --check-prefix=USEAA
+; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=generic | FileCheck %s --check-prefix=CHECK --check-prefix=GENERIC
+
+; Check we use AA during codegen, so can interleave these loads/stores.
+
+; CHECK-LABEL: test
+; GENERIC: ldr
+; GENERIC: str
+; GENERIC: ldr
+; GENERIC: str
+; USEAA: ldr
+; USEAA: ldr
+; USEAA: str
+; USEAA: str
+
+define void @test(i32* nocapture %a, i32* noalias nocapture %b) {
+entry:
+  %0 = load i32, i32* %a, align 4
+  %add = add nsw i32 %0, 10
+  store i32 %add, i32* %a, align 4
+  %1 = load i32, i32* %b, align 4
+  %add2 = add nsw i32 %1, 20
+  store i32 %add2, i32* %b, align 4
+  ret void
+}
+
Index: lib/Target/ARM/ARMSubtarget.h
===================================================================
--- lib/Target/ARM/ARMSubtarget.h
+++ lib/Target/ARM/ARMSubtarget.h
@@ -198,6 +198,9 @@
   /// register allocation.
   bool DisablePostRAScheduler = false;
 
+  /// UseAA - True if using AA during codegen (DAGCombine, MISched, etc)
+  bool UseAA = false;
+
   /// HasThumb2 - True if Thumb2 instructions are supported.
   bool HasThumb2 = false;
 
@@ -723,6 +726,10 @@
   /// True for some subtargets at > -O0.
   bool enablePostRAScheduler() const override;
 
+  /// Enable use of alias analysis during code generation (during MI
+  /// scheduling, DAGCombine, etc.).
+  bool useAA() const override { return UseAA; }
+
   // enableAtomicExpand- True if we need to expand our atomics.
   bool enableAtomicExpand() const override;
 
Index: lib/Target/ARM/ARM.td
===================================================================
--- lib/Target/ARM/ARM.td
+++ lib/Target/ARM/ARM.td
@@ -330,6 +330,10 @@
     "DisablePostRAScheduler", "true",
     "Don't schedule again after register allocation">;
 
+// Enable use of alias analysis during code generation
+def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
+                                    "Use alias analysis during codegen">;
+
 //===----------------------------------------------------------------------===//
 // ARM architecture class
 //
@@ -1006,7 +1010,8 @@
 
 def : ProcessorModel<"cortex-r52", CortexR52Model,      [ARMv8r, ProcR52,
                                                          FeatureUseMISched,
-                                                         FeatureFPAO]>;
+                                                         FeatureFPAO,
+                                                         FeatureUseAA]>;
 
 //===----------------------------------------------------------------------===//
 // Register File Description


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