[llvm] r334490 - [mips] Extend LONG_BRANCH_LUi/ADDiu with extra parameter
Aleksandar Beserminji via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 12 03:23:49 PDT 2018
Author: abeserminji
Date: Tue Jun 12 03:23:49 2018
New Revision: 334490
URL: http://llvm.org/viewvc/llvm-project?rev=334490&view=rev
Log:
[mips] Extend LONG_BRANCH_LUi/ADDiu with extra parameter
Extend LONG_BRANCH_LUi and LONG_BRANCH_ADDiu pseudo instructions with
additional flag, so instead of always lowering to lui %hi(...),
addiu %lo(...) or addiu %hi(...), now they can lower to either %lo, %hi,
%higher or %highest depending on the added flag.
Differential Revision: https://reviews.llvm.org/D47941
Modified:
llvm/trunk/lib/Target/Mips/MipsBranchExpansion.cpp
llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp
llvm/trunk/lib/Target/Mips/MipsMCInstLower.h
llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir
llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir
llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir
llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir
llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir
llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir
llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int.mir
Modified: llvm/trunk/lib/Target/Mips/MipsBranchExpansion.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsBranchExpansion.cpp?rev=334490&r1=334489&r2=334490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsBranchExpansion.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsBranchExpansion.cpp Tue Jun 12 03:23:49 2018
@@ -446,7 +446,7 @@ void MipsBranchExpansion::expandToLongBr
// operands to lowered instructions.
BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT)
- .addMBB(TgtMBB)
+ .addMBB(TgtMBB, MipsII::MO_ABS_HI)
.addMBB(BalTgtMBB);
MachineInstrBuilder BalInstr =
@@ -454,7 +454,7 @@ void MipsBranchExpansion::expandToLongBr
MachineInstrBuilder ADDiuInstr =
BuildMI(*MFp, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT)
.addReg(Mips::AT)
- .addMBB(TgtMBB)
+ .addMBB(TgtMBB, MipsII::MO_ABS_LO)
.addMBB(BalTgtMBB);
if (STI->hasMips32r6()) {
LongBrMBB->insert(Pos, ADDiuInstr);
Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp?rev=334490&r1=334489&r2=334490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.cpp Tue Jun 12 03:23:49 2018
@@ -219,26 +219,77 @@ lowerLongBranchLUi(const MachineInstr *M
// Lower register operand.
OutMI.addOperand(LowerOperand(MI->getOperand(0)));
- // Create %hi($tgt-$baltgt).
- OutMI.addOperand(createSub(MI->getOperand(1).getMBB(),
- MI->getOperand(2).getMBB(),
- MipsMCExpr::MEK_HI));
+ MipsMCExpr::MipsExprKind Kind;
+ unsigned TargetFlags = MI->getOperand(1).getTargetFlags();
+ switch (TargetFlags) {
+ case MipsII::MO_HIGHEST:
+ Kind = MipsMCExpr::MEK_HIGHEST;
+ break;
+ case MipsII::MO_HIGHER:
+ Kind = MipsMCExpr::MEK_HIGHER;
+ break;
+ case MipsII::MO_ABS_HI:
+ Kind = MipsMCExpr::MEK_HI;
+ break;
+ case MipsII::MO_ABS_LO:
+ Kind = MipsMCExpr::MEK_LO;
+ break;
+ default:
+ report_fatal_error("Unexpected flags for lowerLongBranchLUi");
+ }
+
+ if (MI->getNumOperands() == 2) {
+ const MCExpr *Expr =
+ MCSymbolRefExpr::create(MI->getOperand(1).getMBB()->getSymbol(), *Ctx);
+ const MipsMCExpr *MipsExpr = MipsMCExpr::create(Kind, Expr, *Ctx);
+ OutMI.addOperand(MCOperand::createExpr(MipsExpr));
+ } else if (MI->getNumOperands() == 3) {
+ // Create %hi($tgt-$baltgt).
+ OutMI.addOperand(createSub(MI->getOperand(1).getMBB(),
+ MI->getOperand(2).getMBB(), Kind));
+ }
}
-void MipsMCInstLower::lowerLongBranchADDiu(
- const MachineInstr *MI, MCInst &OutMI, int Opcode,
- MipsMCExpr::MipsExprKind Kind) const {
+void MipsMCInstLower::lowerLongBranchADDiu(const MachineInstr *MI,
+ MCInst &OutMI, int Opcode) const {
OutMI.setOpcode(Opcode);
+ MipsMCExpr::MipsExprKind Kind;
+ unsigned TargetFlags = MI->getOperand(2).getTargetFlags();
+ switch (TargetFlags) {
+ case MipsII::MO_HIGHEST:
+ Kind = MipsMCExpr::MEK_HIGHEST;
+ break;
+ case MipsII::MO_HIGHER:
+ Kind = MipsMCExpr::MEK_HIGHER;
+ break;
+ case MipsII::MO_ABS_HI:
+ Kind = MipsMCExpr::MEK_HI;
+ break;
+ case MipsII::MO_ABS_LO:
+ Kind = MipsMCExpr::MEK_LO;
+ break;
+ default:
+ report_fatal_error("Unexpected flags for lowerLongBranchADDiu");
+ }
+
// Lower two register operands.
for (unsigned I = 0, E = 2; I != E; ++I) {
const MachineOperand &MO = MI->getOperand(I);
OutMI.addOperand(LowerOperand(MO));
}
- // Create %lo($tgt-$baltgt) or %hi($tgt-$baltgt).
- OutMI.addOperand(createSub(MI->getOperand(2).getMBB(),
- MI->getOperand(3).getMBB(), Kind));
+ if (MI->getNumOperands() == 3) {
+ // Lower register operand.
+ const MCExpr *Expr =
+ MCSymbolRefExpr::create(MI->getOperand(2).getMBB()->getSymbol(), *Ctx);
+ const MipsMCExpr *MipsExpr = MipsMCExpr::create(Kind, Expr, *Ctx);
+ OutMI.addOperand(MCOperand::createExpr(MipsExpr));
+ } else if (MI->getNumOperands() == 4) {
+ // Create %lo($tgt-$baltgt) or %hi($tgt-$baltgt).
+ OutMI.addOperand(createSub(MI->getOperand(2).getMBB(),
+ MI->getOperand(3).getMBB(), Kind));
+ }
}
bool MipsMCInstLower::lowerLongBranch(const MachineInstr *MI,
@@ -250,16 +301,10 @@ bool MipsMCInstLower::lowerLongBranch(co
lowerLongBranchLUi(MI, OutMI);
return true;
case Mips::LONG_BRANCH_ADDiu:
- lowerLongBranchADDiu(MI, OutMI, Mips::ADDiu, MipsMCExpr::MEK_LO);
+ lowerLongBranchADDiu(MI, OutMI, Mips::ADDiu);
return true;
case Mips::LONG_BRANCH_DADDiu:
- unsigned TargetFlags = MI->getOperand(2).getTargetFlags();
- if (TargetFlags == MipsII::MO_ABS_HI)
- lowerLongBranchADDiu(MI, OutMI, Mips::DADDiu, MipsMCExpr::MEK_HI);
- else if (TargetFlags == MipsII::MO_ABS_LO)
- lowerLongBranchADDiu(MI, OutMI, Mips::DADDiu, MipsMCExpr::MEK_LO);
- else
- report_fatal_error("Unexpected flags for LONG_BRANCH_DADDiu");
+ lowerLongBranchADDiu(MI, OutMI, Mips::DADDiu);
return true;
}
}
Modified: llvm/trunk/lib/Target/Mips/MipsMCInstLower.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMCInstLower.h?rev=334490&r1=334489&r2=334490&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMCInstLower.h (original)
+++ llvm/trunk/lib/Target/Mips/MipsMCInstLower.h Tue Jun 12 03:23:49 2018
@@ -44,8 +44,8 @@ private:
MCOperand createSub(MachineBasicBlock *BB1, MachineBasicBlock *BB2,
MipsMCExpr::MipsExprKind Kind) const;
void lowerLongBranchLUi(const MachineInstr *MI, MCInst &OutMI) const;
- void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI, int Opcode,
- MipsMCExpr::MipsExprKind Kind) const;
+ void lowerLongBranchADDiu(const MachineInstr *MI, MCInst &OutMI,
+ int Opcode) const;
bool lowerLongBranch(const MachineInstr *MI, MCInst &OutMI) const;
};
Modified: llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir?rev=334490&r1=334489&r2=334490&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir Tue Jun 12 03:23:49 2018
@@ -98,9 +98,9 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
Modified: llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir?rev=334490&r1=334489&r2=334490&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir Tue Jun 12 03:23:49 2018
@@ -92,8 +92,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
@@ -184,8 +184,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
Modified: llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir?rev=334490&r1=334489&r2=334490&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir Tue Jun 12 03:23:49 2018
@@ -99,9 +99,9 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
@@ -203,9 +203,9 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
Modified: llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir?rev=334490&r1=334489&r2=334490&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir Tue Jun 12 03:23:49 2018
@@ -99,8 +99,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
@@ -199,8 +199,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2.entry:
; PIC: successors: %bb.4(0x80000000)
Modified: llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir?rev=334490&r1=334489&r2=334490&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-microMIPS.mir Tue Jun 12 03:23:49 2018
@@ -153,9 +153,9 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -248,9 +248,9 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -343,9 +343,9 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -438,9 +438,9 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -533,9 +533,9 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -624,9 +624,9 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -719,9 +719,9 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -814,9 +814,9 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR_MM %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
Modified: llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir?rev=334490&r1=334489&r2=334490&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-micromipsr6.mir Tue Jun 12 03:23:49 2018
@@ -195,8 +195,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -282,8 +282,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -369,8 +369,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -456,8 +456,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -543,8 +543,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -630,8 +630,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -717,8 +717,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -804,8 +804,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -891,8 +891,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -978,8 +978,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -1065,8 +1065,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -1152,8 +1152,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC_MMR6 %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
Modified: llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir?rev=334490&r1=334489&r2=334490&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int-mipsr6.mir Tue Jun 12 03:23:49 2018
@@ -195,8 +195,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -282,8 +282,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -369,8 +369,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -456,8 +456,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -543,8 +543,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -630,8 +630,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -717,8 +717,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -804,8 +804,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -891,8 +891,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -978,8 +978,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -1065,8 +1065,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -1152,8 +1152,8 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: BALC %bb.2, implicit-def $ra
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
Modified: llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int.mir?rev=334490&r1=334489&r2=334490&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/longbranch/branch-limits-int.mir Tue Jun 12 03:23:49 2018
@@ -137,9 +137,9 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -236,9 +236,9 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -335,9 +335,9 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -434,9 +434,9 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -533,9 +533,9 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
@@ -632,9 +632,9 @@ body: |
; PIC: successors: %bb.2(0x80000000)
; PIC: $sp = ADDiu $sp, -8
; PIC: SW $ra, $sp, 0
- ; PIC: $at = LONG_BRANCH_LUi %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_LUi target-flags(mips-abs-hi) %bb.4, %bb.2
; PIC: BAL_BR %bb.2, implicit-def $ra {
- ; PIC: $at = LONG_BRANCH_ADDiu $at, %bb.4, %bb.2
+ ; PIC: $at = LONG_BRANCH_ADDiu $at, target-flags(mips-abs-lo) %bb.4, %bb.2
; PIC: }
; PIC: bb.2 (%ir-block.0):
; PIC: successors: %bb.4(0x80000000)
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