[llvm] r334488 - [AArch64] Audit on rL333879 to fix FP16 64bit bitpatterns

[Luke Geeson via llvm-commits]

Author: lukegeeson
Date: Tue Jun 12 02:35:20 2018
New Revision: 334488

URL: http://llvm.org/viewvc/llvm-project?rev=334488&view=rev
Log:
[AArch64] Audit on rL333879 to fix FP16 64bit bitpatterns

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td

Modified: llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td?rev=334488&r1=334487&r2=334488&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64InstrFormats.td Tue Jun 12 02:35:20 2018
@@ -7938,10 +7938,10 @@ multiclass SIMDFPScalarRShift<bit U, bit
     let Inst{21-16} = imm{5-0};
     let Inst{23-22} = 0b11;
   }
-  def DHr : BaseSIMDScalarShift<U, opc, {?,?,?,?,?,?,?},
+  def DHr : BaseSIMDScalarShift<U, opc, {1,1,1,?,?,?,?},
                                 FPR64, FPR16, vecshiftR64, asm, []> {
     let Inst{21-16} = imm{5-0};
-    let Inst{23-22} = 0b11;
+    let Inst{23-22} = 0b01;
     let Inst{31} = 1;
   }
   def h : BaseSIMDScalarShift<U, opc, {0,0,1,?,?,?,?},