[PATCH] D48028: [X86] Fix NOOP sched overrides on BDW/HSW/SKL.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

The only way they would wait for a data dependency is if they actually went into the RS. And I would expect the only way out of the RS is to go out an execution port. I wonder if Intel failed to update the optimization manual after some uarch change. If I remember from my days in hardware design long ago during Nehalem, the only uop that was removed during rename was FXCH. So maybe some things changed during Sandy Bridge when the phyiscal register file was added. Or when move elimimination was added.


Repository:
  rL LLVM

https://reviews.llvm.org/D48028