[PATCH] D47568: [Power9] Do the add-imm peephole for pseudo instruction DFLOADf32/DFLOADf64 and the store pair

[Qing Shan Zhang via Phabricator via llvm-commits]

steven.zhang marked an inline comment as done.
steven.zhang added inline comments.


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Comment at: llvm/test/CodeGen/PowerPC/toc-float.ll:65
+
+; TODO - We could do some peephole post RA to optimize it as LFD
+; CHECK-LABEL: doubleLargeConstantArray
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steven.zhang wrote:
> nemanjai wrote:
> > This comment is unclear to me. I'm not sure how we could use a D-Form instruction when the offset doesn't fit in the displacement field. In any case, clarify the comment or remove it.
> LFD didn't have the alignment restrict while LXSD has. When TOC_Entry is lowing, we assume that, the disp must be multiple of 4, which in fact, is not necessary for LFD. Therefore, we could do it post RA. For this case, LFD 32768[REG] is valid. 
Sorry, please just ignore this comment, as I didn't realize that, the imm for LFD is signed, whose range is -32768 ~ 32767. LFD 32768[REG] is invalid. And this has nothing to do with alignment. 


https://reviews.llvm.org/D47568