[PATCH] D47907: [tablegen] Improve performance on *GenRegisterInfo.inc by replacing SparseVector with BitVector. NFC

[Justin Bogner via Phabricator via llvm-commits]

bogner accepted this revision.
bogner added a comment.
This revision is now accepted and ready to land.

This makes a lot of sense, especially given that the change to use SparseBitVector here instead of std::set specifically called out that this was to improve cases where there were dense register files. LGTM.


Repository:
  rL LLVM

https://reviews.llvm.org/D47907