[llvm] r334195 - [PowerPC] avoid unprofitable Repl32 flag in BitPermutationSelector

[Hiroshi Inoue via llvm-commits]

Author: inouehrs
Date: Thu Jun  7 06:21:14 2018
New Revision: 334195

URL: http://llvm.org/viewvc/llvm-project?rev=334195&view=rev
Log:
[PowerPC] avoid unprofitable Repl32 flag in BitPermutationSelector

BitPermutationSelector sets Repl32 flag for bit groups which can be (potentially) benefit from 32-bit rotate-and-mask instructions with bit replication, i.e. rlwinm/rlwimi copies lower 32 bits into upper 32 bits on 64-bit PowerPC before rotation.
However, enforcing 32-bit instruction sometimes results in redundant generated code.
For example, the following simple code is compiled into rotldi + rlwimi while it can be compiled into only rldimi instruction if Repl32 flag is not set on the bit group for (a & 0xFFFFFFFF).

uint64_t func(uint64_t a, uint64_t b) {
	return (a & 0xFFFFFFFF) | (b << 32) ;
}

To avoid such problem, this patch checks the potential benefit of Repl32 flag before setting it. If a bit group does not require rotation (i.e. RLAmt == 0) and won't be merged into another group, we do not benefit from Repl32 flag on this group.

Differential Revision: https://reviews.llvm.org/D47867


Modified:
    llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
    llvm/trunk/test/CodeGen/PowerPC/bperm.ll

Modified: llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp?rev=334195&r1=334194&r2=334195&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelDAGToDAG.cpp Thu Jun  7 06:21:14 2018
@@ -1450,6 +1450,20 @@ class BitPermutationSelector {
     };
 
     for (auto &BG : BitGroups) {
+      // If this bit group has RLAmt of 0 and will not be merged with
+      // another bit group, we don't benefit from Repl32. We don't mark
+      // such group to give more freedom for later instruction selection.
+      if (BG.RLAmt == 0) {
+        auto PotentiallyMerged = [this](BitGroup & BG) {
+          for (auto &BG2 : BitGroups)
+            if (&BG != &BG2 && BG.V == BG2.V &&
+                (BG2.RLAmt == 0 || BG2.RLAmt == 32))
+              return true;
+          return false;
+        };
+        if (!PotentiallyMerged(BG))
+          continue;
+      }
       if (BG.StartIdx < 32 && BG.EndIdx < 32) {
         if (IsAllLow32(BG)) {
           if (BG.RLAmt >= 32) {

Modified: llvm/trunk/test/CodeGen/PowerPC/bperm.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/PowerPC/bperm.ll?rev=334195&r1=334194&r2=334195&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/PowerPC/bperm.ll (original)
+++ llvm/trunk/test/CodeGen/PowerPC/bperm.ll Thu Jun  7 06:21:14 2018
@@ -271,6 +271,18 @@ entry:
 ; CHECK: blr
 }
 
+define i64 @test16(i64 %a, i64 %b) #0 {
+entry:
+  %and = and i64 %a, 4294967295
+  %shl = shl i64 %b, 32
+  %or = or i64 %and, %shl
+  ret i64 %or
+
+; CHECK-LABEL: @test16
+; CHECK: rldimi 3, 4, 32, 0
+; CHECK: blr
+}
+
 ; Function Attrs: nounwind readnone
 declare i32 @llvm.bswap.i32(i32) #0
 declare i64 @llvm.bswap.i64(i64) #0