[PATCH] D46356: [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles.

[Clement Courbet via Phabricator via llvm-commits]

courbet added inline comments.


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM1.td:343
                                                      let NumMicroOps = 3;
-                                                     let ResourceCycles = [6]; }
+                                                     let ResourceCycles = [6, 1, 1]; }
 def M1WriteVLDJ    : SchedWriteRes<[M1UnitL,
----------------
evandro wrote:
> [2, 2, 2]
I set ` NumMicroOps = 6` to be consistent. Is that OK ?


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM1.td:349
                                                      let NumMicroOps = 4;
-                                                     let ResourceCycles = [4]; }
+                                                     let ResourceCycles = [4, 1, 1, 1]; }
 def M1WriteVLDK    : SchedWriteRes<[M1UnitL,
----------------
evandro wrote:
> [2, 1, 1, 1]
`NumMicroOps = 5`


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM1.td:356
                                                      let NumMicroOps = 5;
-                                                     let ResourceCycles = [4]; }
+                                                     let ResourceCycles = [4, 1, 1, 1, 1]; }
 def M1WriteVLDL    : SchedWriteRes<[M1UnitL,
----------------
evandro wrote:
> [2, 1, 1, 1, 1]
`NumMicroOps = 6`


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM1.td:377
                                                      let NumMicroOps = 4;
-                                                     let ResourceCycles = [7]; }
+                                                     let ResourceCycles = [7, 1, 1, 1]; }
 def M1WriteVSTA    : WriteSequence<[WriteVST], 2>;
----------------
evandro wrote:
> [2, 1, 2, 1]
`NumMicroOps = 6`


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM1.td:392
                                                      let NumMicroOps = 3;
-                                                     let ResourceCycles = [8]; }
+                                                     let ResourceCycles = [8, 1, 1, 1, 1]; }
 def M1WriteVSTF    : SchedWriteRes<[M1UnitNALU,
----------------
evandro wrote:
> [7, 1, 1, 1, 1]
NumMicroOps = 11


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM1.td:401
                                                       let NumMicroOps = 5;
-                                                      let ResourceCycles = [15]; }
+                                                      let ResourceCycles = [15, 1, 1, 1, 1, 1, 1]; }
 def M1WriteVSTG    : SchedWriteRes<[M1UnitNALU,
----------------
evandro wrote:
> [1, 7, 1, 7, 1, 1, 1]
ditto


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM1.td:412
                                                       let NumMicroOps = 6;
-                                                      let ResourceCycles = [16]; }
+                                                      let ResourceCycles = [16, 1, 1, 1, 1, 1, 1, 1, 1]; }
 def M1WriteVSTH    : SchedWriteRes<[M1UnitNALU,
----------------
evandro wrote:
> [1, 7, 1, 7, 1, 1, 1, 1, 1]
ditto


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM1.td:419
                                                        let NumMicroOps = 4;
-                                                       let ResourceCycles = [14]; }
+                                                       let ResourceCycles = [14, 1, 1, 1, 1]; }
 def M1WriteVSTI    : SchedWriteRes<[M1UnitNALU,
----------------
evandro wrote:
> [1, 7, 1, 7, 1]
ditto


================
Comment at: lib/Target/AArch64/AArch64SchedExynosM1.td:432
                                                        let NumMicroOps = 7;
-                                                       let ResourceCycles = [17]; }
+                                                       let ResourceCycles = [17, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1]; }
 
----------------
evandro wrote:
> [1, 7, 1, 7, 1, 1, 1, 1, 1, 1, 1]
ditto


Repository:
  rL LLVM

https://reviews.llvm.org/D46356