[llvm] r334123 - [Hexagon] Implement vector-pair zero as V6_vsubw_dv

[Krzysztof Parzyszek via llvm-commits]

Author: kparzysz
Date: Wed Jun  6 12:34:40 2018
New Revision: 334123

URL: http://llvm.org/viewvc/llvm-project?rev=334123&view=rev
Log:
[Hexagon] Implement vector-pair zero as V6_vsubw_dv

Added:
    llvm/trunk/test/CodeGen/Hexagon/autohvx/vdd0.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
    llvm/trunk/lib/Target/Hexagon/HexagonPatternsHVX.td
    llvm/trunk/lib/Target/Hexagon/HexagonPseudo.td

Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=334123&r1=334122&r2=334123&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Wed Jun  6 12:34:40 2018
@@ -1153,6 +1153,14 @@ bool HexagonInstrInfo::expandPostRAPseud
       MBB.erase(MI);
       return true;
     }
+    case Hexagon::PS_vdd0: {
+      unsigned Vd = MI.getOperand(0).getReg();
+      BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd)
+        .addReg(Vd, RegState::Undef)
+        .addReg(Vd, RegState::Undef);
+      MBB.erase(MI);
+      return true;
+    }
     case Hexagon::PS_vmulw: {
       // Expand a 64-bit vector multiply into 2 32-bit scalar multiplies.
       unsigned DstReg = MI.getOperand(0).getReg();

Modified: llvm/trunk/lib/Target/Hexagon/HexagonPatternsHVX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPatternsHVX.td?rev=334123&r1=334122&r2=334123&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPatternsHVX.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPatternsHVX.td Wed Jun  6 12:34:40 2018
@@ -185,10 +185,13 @@ let Predicates = [UseHVX] in {
   def: Pat<(VecI8   vzero), (V6_vd0)>;
   def: Pat<(VecI16  vzero), (V6_vd0)>;
   def: Pat<(VecI32  vzero), (V6_vd0)>;
-  // Use V6_vsubw_dv instead.
-  def: Pat<(VecPI8  vzero), (Combinev (V6_vd0), (V6_vd0))>;
-  def: Pat<(VecPI16 vzero), (Combinev (V6_vd0), (V6_vd0))>;
-  def: Pat<(VecPI32 vzero), (Combinev (V6_vd0), (V6_vd0))>;
+  def: Pat<(VecPI8  vzero), (PS_vdd0)>;
+  def: Pat<(VecPI16 vzero), (PS_vdd0)>;
+  def: Pat<(VecPI32 vzero), (PS_vdd0)>;
+
+  def: Pat<(concat_vectors  (VecI8 vzero),  (VecI8 vzero)), (PS_vdd0)>;
+  def: Pat<(concat_vectors (VecI16 vzero), (VecI16 vzero)), (PS_vdd0)>;
+  def: Pat<(concat_vectors (VecI32 vzero), (VecI32 vzero)), (PS_vdd0)>;
 
   def: Pat<(VecPI8 (concat_vectors HVI8:$Vs, HVI8:$Vt)),
            (Combinev HvxVR:$Vt, HvxVR:$Vs)>;

Modified: llvm/trunk/lib/Target/Hexagon/HexagonPseudo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPseudo.td?rev=334123&r1=334122&r2=334123&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPseudo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPseudo.td Wed Jun  6 12:34:40 2018
@@ -461,6 +461,8 @@ let hasSideEffects = 0, isReMaterializab
                  V6_veqw.Itinerary, TypeCVI_VA>;
   def PS_qfalse: InstHexagon<(outs HvxQR:$Qd), (ins), "", [], "",
                  V6_vgtw.Itinerary, TypeCVI_VA>;
+  def PS_vdd0:   InstHexagon<(outs HvxWR:$Vd), (ins), "", [], "",
+                 V6_vsubw_dv.Itinerary, TypeCVI_VA_DV>;
 }
 
 // Store predicate.

Added: llvm/trunk/test/CodeGen/Hexagon/autohvx/vdd0.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/autohvx/vdd0.ll?rev=334123&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/autohvx/vdd0.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/autohvx/vdd0.ll Wed Jun  6 12:34:40 2018
@@ -0,0 +1,41 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; CHECK-LABEL: f0:
+; CHECK: v1:0.w = vsub(v1:0.w,v1:0.w)
+define <128 x i8> @f0() #0 {
+  ret <128 x i8> zeroinitializer
+}
+
+; CHECK-LABEL: f1:
+; CHECK: v1:0.w = vsub(v1:0.w,v1:0.w)
+define <64 x i16> @f1() #0 {
+  ret <64 x i16> zeroinitializer
+}
+
+; CHECK-LABEL: f2:
+; CHECK: v1:0.w = vsub(v1:0.w,v1:0.w)
+define <32 x i32> @f2() #0 {
+  ret <32 x i32> zeroinitializer
+}
+
+; CHECK-LABEL: f3:
+; CHECK: v1:0.w = vsub(v1:0.w,v1:0.w)
+define <256 x i8> @f3() #1 {
+  ret <256 x i8> zeroinitializer
+}
+
+; CHECK-LABEL: f4:
+; CHECK: v1:0.w = vsub(v1:0.w,v1:0.w)
+define <128 x i16> @f4() #1 {
+  ret <128 x i16> zeroinitializer
+}
+
+; CHECK-LABEL: f5:
+; CHECK: v1:0.w = vsub(v1:0.w,v1:0.w)
+define <64 x i32> @f5() #1 {
+  ret <64 x i32> zeroinitializer
+}
+
+attributes #0 = { readnone nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
+attributes #1 = { readnone nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
+