[PATCH] D47823: AMDGPU: Try a lot harder to emit scalar loads

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:1104
+    SDValue ShiftAmt = DAG.getConstant(OffsetDiff * 8, SL, MVT::i32);
+    SDValue Extract = DAG.getNode(ISD::SRL, SL, MVT::i32, Load, ShiftAmt);
+
----------------
rampitec wrote:
> It can happen that offset diff is zero and then shift is not needed. Say you have kernarg layout: i32 a, i16 b, i16 c. For 'b' align will be 2, but offset will be 4.
getNode already avoids creating a shift if the passed offset is 0


================
Comment at: lib/Target/AMDGPU/SIISelLowering.cpp:5364
+                                MVT::i32, SL, Ld->getChain(), Ptr,
+                                DAG.getUNDEF(Ptr.getValueType()),
+                                Ld->getPointerInfo(), MVT::i32,
----------------
rampitec wrote:
> Why do not you want to get pointer, pointer info, AA and the rest from original load?
Question wording is broken.

Everything remains the same, except the memory and possibly result type. I don't think the pointer info access size needs to increase, although I'm not 100% sure


https://reviews.llvm.org/D47823