[llvm] r334043 - [Hexagon] Add pattern to generate 64-bit neg instruction

Krzysztof Parzyszek via llvm-commits llvm-commits at lists.llvm.org
Tue Jun 5 12:52:39 PDT 2018


Author: kparzysz
Date: Tue Jun  5 12:52:39 2018
New Revision: 334043

URL: http://llvm.org/viewvc/llvm-project?rev=334043&view=rev
Log:
[Hexagon] Add pattern to generate 64-bit neg instruction

Added:
    llvm/trunk/test/CodeGen/Hexagon/neg.ll
Removed:
    llvm/trunk/test/CodeGen/Hexagon/neg-op.ll
Modified:
    llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td

Modified: llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td?rev=334043&r1=334042&r2=334043&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td Tue Jun  5 12:52:39 2018
@@ -1157,10 +1157,11 @@ def: Pat<(shl V4I16:$b, (v4i16 (HexagonV
 // --(9) Arithmetic/bitwise ----------------------------------------------
 //
 
-def: Pat<(abs I32:$Rs), (A2_abs   I32:$Rs)>;
-def: Pat<(abs I64:$Rs), (A2_absp  I64:$Rs)>;
-def: Pat<(not I32:$Rs), (A2_subri -1, I32:$Rs)>;
-def: Pat<(not I64:$Rs), (A2_notp  I64:$Rs)>;
+def: Pat<(abs  I32:$Rs), (A2_abs   I32:$Rs)>;
+def: Pat<(abs  I64:$Rs), (A2_absp  I64:$Rs)>;
+def: Pat<(not  I32:$Rs), (A2_subri -1, I32:$Rs)>;
+def: Pat<(not  I64:$Rs), (A2_notp  I64:$Rs)>;
+def: Pat<(ineg I64:$Rs), (A2_negp  I64:$Rs)>;
 
 let Predicates = [HasV5T] in {
   def: Pat<(fabs F32:$Rs), (S2_clrbit_i    F32:$Rs, 31)>;

Removed: llvm/trunk/test/CodeGen/Hexagon/neg-op.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/neg-op.ll?rev=334042&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/neg-op.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/neg-op.ll (removed)
@@ -1,14 +0,0 @@
-; RUN: llc -march=hexagon < %s | FileCheck %s
-; CHECK: r{{[0-9]+}} = sub(#0,r{{[0-9]+}})
-
-; Function Attrs: nounwind
-define i32 @f0(i32 %a0) #0 {
-b0:
-  %v0 = alloca i32, align 4
-  store i32 %a0, i32* %v0, align 4
-  %v1 = load i32, i32* %v0, align 4
-  %v2 = sub nsw i32 0, %v1
-  ret i32 %v2
-}
-
-attributes #0 = { nounwind }

Added: llvm/trunk/test/CodeGen/Hexagon/neg.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/neg.ll?rev=334043&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/neg.ll (added)
+++ llvm/trunk/test/CodeGen/Hexagon/neg.ll Tue Jun  5 12:52:39 2018
@@ -0,0 +1,17 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; CHECK-LABEL: f0:
+; CHECK: r0 = sub(#0,r0)
+define i32 @f0(i32 %a0) #0 {
+  %v0 = sub i32 0, %a0
+  ret i32 %v0
+}
+
+; CHECK-LABEL: f1:
+; CHECK: r1:0 = neg(r1:0)
+define i64 @f1(i64 %a0) #0 {
+  %v0 = sub i64 0, %a0
+  ret i64 %v0
+}
+
+attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" }




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