[llvm] r334028 - [llvm-mca] Correctly update the CyclesLeft of a register read in the presence of partial register updates.
Andrea Di Biagio via llvm-commits
llvm-commits at lists.llvm.org
Tue Jun 5 10:12:03 PDT 2018
Author: adibiagio
Date: Tue Jun 5 10:12:02 2018
New Revision: 334028
URL: http://llvm.org/viewvc/llvm-project?rev=334028&view=rev
Log:
[llvm-mca] Correctly update the CyclesLeft of a register read in the presence of partial register updates.
This patch fixe the logic in ReadState::cycleEvent(). That method was not
correctly updating field `TotalCycles`.
Added extra code comments in class ReadState to better describe each field.
Added:
llvm/trunk/test/tools/llvm-mca/X86/BtVer2/partial-reg-update.s
Modified:
llvm/trunk/test/tools/llvm-mca/X86/BtVer2/zero-idioms.s
llvm/trunk/tools/llvm-mca/Instruction.cpp
llvm/trunk/tools/llvm-mca/Instruction.h
Added: llvm/trunk/test/tools/llvm-mca/X86/BtVer2/partial-reg-update.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/BtVer2/partial-reg-update.s?rev=334028&view=auto
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/BtVer2/partial-reg-update.s (added)
+++ llvm/trunk/test/tools/llvm-mca/X86/BtVer2/partial-reg-update.s Tue Jun 5 10:12:02 2018
@@ -0,0 +1,44 @@
+# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
+# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -iterations=1 -resource-pressure=false -timeline < %s | FileCheck %s
+
+imul %ax, %cx
+add %al, %cl
+add %ecx, %ebx
+
+# CHECK: Iterations: 1
+# CHECK-NEXT: Instructions: 3
+# CHECK-NEXT: Total Cycles: 8
+# CHECK-NEXT: Dispatch Width: 2
+# CHECK-NEXT: IPC: 0.38
+# CHECK-NEXT: Block RThroughput: 2.0
+
+# CHECK: Instruction Info:
+# CHECK-NEXT: [1]: #uOps
+# CHECK-NEXT: [2]: Latency
+# CHECK-NEXT: [3]: RThroughput
+# CHECK-NEXT: [4]: MayLoad
+# CHECK-NEXT: [5]: MayStore
+# CHECK-NEXT: [6]: HasSideEffects
+
+# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
+# CHECK-NEXT: 2 3 1.00 imulw %ax, %cx
+# CHECK-NEXT: 1 1 0.50 addb %al, %cl
+# CHECK-NEXT: 1 1 0.50 addl %ecx, %ebx
+
+# CHECK: Timeline view:
+# CHECK-NEXT: Index 01234567
+
+# CHECK: [0,0] DeeeER . imulw %ax, %cx
+# CHECK-NEXT: [0,1] .D==eER. addb %al, %cl
+# CHECK-NEXT: [0,2] .D===eER addl %ecx, %ebx
+
+# CHECK: Average Wait times (based on the timeline view):
+# CHECK-NEXT: [0]: Executions
+# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
+# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
+# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
+
+# CHECK: [0] [1] [2] [3]
+# CHECK-NEXT: 0. 1 1.0 1.0 0.0 imulw %ax, %cx
+# CHECK-NEXT: 1. 1 3.0 0.0 0.0 addb %al, %cl
+# CHECK-NEXT: 2. 1 4.0 0.0 0.0 addl %ecx, %ebx
Modified: llvm/trunk/test/tools/llvm-mca/X86/BtVer2/zero-idioms.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/tools/llvm-mca/X86/BtVer2/zero-idioms.s?rev=334028&r1=334027&r2=334028&view=diff
==============================================================================
--- llvm/trunk/test/tools/llvm-mca/X86/BtVer2/zero-idioms.s (original)
+++ llvm/trunk/test/tools/llvm-mca/X86/BtVer2/zero-idioms.s Tue Jun 5 10:12:02 2018
@@ -150,4 +150,3 @@ vpxor %xmm3, %xmm3, %xmm5
# CHECK-NEXT: 6. 5 0.0 0.0 0.0 vxorps %xmm4, %xmm4, %xmm5
# CHECK-NEXT: 7. 5 0.0 0.0 0.0 vxorpd %xmm1, %xmm1, %xmm3
# CHECK-NEXT: 8. 5 0.0 0.0 0.0 vpxor %xmm3, %xmm3, %xmm5
-
Modified: llvm/trunk/tools/llvm-mca/Instruction.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/Instruction.cpp?rev=334028&r1=334027&r2=334028&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/Instruction.cpp (original)
+++ llvm/trunk/tools/llvm-mca/Instruction.cpp Tue Jun 5 10:12:02 2018
@@ -41,7 +41,7 @@ void WriteState::onInstructionIssued() {
// Update the number of cycles left based on the WriteDescriptor info.
CyclesLeft = WD.Latency;
- // Now that the time left before write-back is know, notify
+ // Now that the time left before write-back is known, notify
// all the users.
for (const std::pair<ReadState *, int> &User : Users) {
ReadState *RS = User.first;
@@ -73,16 +73,18 @@ void WriteState::cycleEvent() {
}
void ReadState::cycleEvent() {
- // If CyclesLeft is unknown, then bail out immediately.
- if (CyclesLeft == UNKNOWN_CYCLES)
+ // Update the total number of cycles.
+ if (DependentWrites && TotalCycles) {
+ --TotalCycles;
return;
+ }
- // If there are still dependent writes, or we reached cycle zero,
- // then just exit.
- if (DependentWrites || CyclesLeft == 0)
+ // Bail out immediately if we don't know how many cycles are left.
+ if (CyclesLeft == UNKNOWN_CYCLES)
return;
- CyclesLeft--;
+ if (CyclesLeft)
+ --CyclesLeft;
}
#ifndef NDEBUG
Modified: llvm/trunk/tools/llvm-mca/Instruction.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-mca/Instruction.h?rev=334028&r1=334027&r2=334028&view=diff
==============================================================================
--- llvm/trunk/tools/llvm-mca/Instruction.h (original)
+++ llvm/trunk/tools/llvm-mca/Instruction.h Tue Jun 5 10:12:02 2018
@@ -165,9 +165,20 @@ public:
/// writes only partially update the register associated to this read.
class ReadState {
const ReadDescriptor &RD;
+ // Physical register identified associated to this read.
unsigned RegisterID;
+ // Number of writes that contribute to the definition of RegisterID.
+ // In the absence of partial register updates, the number of DependentWrites
+ // cannot be more than one.
unsigned DependentWrites;
+ // Number of cycles left before RegisterID can be read. This value depends on
+ // the latency of all the dependent writes. It defaults to UNKNOWN_CYCLES.
+ // It gets set to the value of field TotalCycles only when the 'CyclesLeft' of
+ // every dependent write is known.
int CyclesLeft;
+ // This field is updated on every writeStartEvent(). When the number of
+ // dependent writes (i.e. field DependentWrite) is zero, this value is
+ // propagated to field CyclesLeft.
unsigned TotalCycles;
public:
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