[llvm] r333984 - [X86] Make all instructions that operate on MMX types, but were added after the initial MMX support via one of the SSE features flags make them require the MMX feature as well.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Jun 4 23:20:06 PDT 2018
Author: ctopper
Date: Mon Jun 4 23:20:06 2018
New Revision: 333984
URL: http://llvm.org/viewvc/llvm-project?rev=333984&view=rev
Log:
[X86] Make all instructions that operate on MMX types, but were added after the initial MMX support via one of the SSE features flags make them require the MMX feature as well.
Passing -mattr=-mmx needs to disable these instructions since the MMX register class won't have been set up. But we don't want -mattr=-mmx to disable SSE so we have to do it separately.
Modified:
llvm/trunk/lib/Target/X86/X86InstrFormats.td
llvm/trunk/lib/Target/X86/X86InstrMMX.td
llvm/trunk/test/CodeGen/X86/pr23246.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrFormats.td?rev=333984&r1=333983&r2=333984&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrFormats.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrFormats.td Mon Jun 4 23:20:06 2018
@@ -518,8 +518,8 @@ class PI<bits<8> o, Format F, dag outs,
class MMXPI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern,
Domain d>
: I<o, F, outs, ins, asm, pattern, d> {
- let Predicates = !if(!eq(OpPrefix.Value, PD.Value), [HasSSE2],
- [HasSSE1]);
+ let Predicates = !if(!eq(OpPrefix.Value, PD.Value), [HasMMX, HasSSE2],
+ [HasMMX, HasSSE1]);
}
// PIi8 - SSE 1 & 2 packed instructions with immediate
@@ -627,10 +627,10 @@ class S2I<bits<8> o, Format F, dag outs,
: I<o, F, outs, ins, asm, pattern>, PD, Requires<[UseSSE2]>;
class MMXSDIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern>
- : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasSSE2]>;
+ : Ii8<o, F, outs, ins, asm, pattern>, XD, Requires<[HasMMX, HasSSE2]>;
class MMXS2SIi8<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern>
- : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE2]>;
+ : Ii8<o, F, outs, ins, asm, pattern>, XS, Requires<[HasMMX, HasSSE2]>;
// SSE3 Instruction Templates:
//
@@ -674,11 +674,11 @@ class SS3AI<bits<8> o, Format F, dag out
class MMXSS38I<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern>
: I<o, F, outs, ins, asm, pattern, SSEPackedInt>, T8PS,
- Requires<[HasSSSE3]>;
+ Requires<[HasMMX, HasSSSE3]>;
class MMXSS3AI<bits<8> o, Format F, dag outs, dag ins, string asm,
list<dag> pattern>
: Ii8<o, F, outs, ins, asm, pattern, SSEPackedInt>, TAPS,
- Requires<[HasSSSE3]>;
+ Requires<[HasMMX, HasSSSE3]>;
// SSE4.1 Instruction Templates:
//
Modified: llvm/trunk/lib/Target/X86/X86InstrMMX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrMMX.td?rev=333984&r1=333983&r2=333984&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrMMX.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrMMX.td Mon Jun 4 23:20:06 2018
@@ -269,7 +269,7 @@ def MMX_MOVFR642Qrr: MMXSDIi8<0xD6, MRMS
}
} // SchedRW
-let Predicates = [HasSSE1] in
+let Predicates = [HasMMX, HasSSE1] in
def MMX_MOVNTQmr : MMXI<0xE7, MRMDestMem, (outs), (ins i64mem:$dst, VR64:$src),
"movntq\t{$src, $dst|$dst, $src}",
[(int_x86_mmx_movnt_dq addr:$dst, VR64:$src)]>,
@@ -299,7 +299,7 @@ defm MMX_PADDW : MMXI_binop_rm_int<0xFD,
SchedWriteVecALU.MMX, 1>;
defm MMX_PADDD : MMXI_binop_rm_int<0xFE, "paddd", int_x86_mmx_padd_d,
SchedWriteVecALU.MMX, 1>;
-let Predicates = [HasSSE2] in
+let Predicates = [HasMMX, HasSSE2] in
defm MMX_PADDQ : MMXI_binop_rm_int<0xD4, "paddq", int_x86_mmx_padd_q,
SchedWriteVecALU.MMX, 1>;
defm MMX_PADDSB : MMXI_binop_rm_int<0xEC, "paddsb" , int_x86_mmx_padds_b,
@@ -326,7 +326,7 @@ defm MMX_PSUBW : MMXI_binop_rm_int<0xF9,
SchedWriteVecALU.MMX>;
defm MMX_PSUBD : MMXI_binop_rm_int<0xFA, "psubd", int_x86_mmx_psub_d,
SchedWriteVecALU.MMX>;
-let Predicates = [HasSSE2] in
+let Predicates = [HasMMX, HasSSE2] in
defm MMX_PSUBQ : MMXI_binop_rm_int<0xFB, "psubq", int_x86_mmx_psub_q,
SchedWriteVecALU.MMX>;
@@ -353,10 +353,10 @@ defm MMX_PMULLW : MMXI_binop_rm_int<0xD
defm MMX_PMULHW : MMXI_binop_rm_int<0xE5, "pmulhw", int_x86_mmx_pmulh_w,
SchedWriteVecIMul.MMX, 1>;
-let Predicates = [HasSSE1] in
+let Predicates = [HasMMX, HasSSE1] in
defm MMX_PMULHUW : MMXI_binop_rm_int<0xE4, "pmulhuw", int_x86_mmx_pmulhu_w,
SchedWriteVecIMul.MMX, 1>;
-let Predicates = [HasSSE2] in
+let Predicates = [HasMMX, HasSSE2] in
defm MMX_PMULUDQ : MMXI_binop_rm_int<0xF4, "pmuludq", int_x86_mmx_pmulu_dq,
SchedWriteVecIMul.MMX, 1>;
defm MMX_PMULHRSW : SS3I_binop_rm_int_mm<0x0B, "pmulhrsw",
@@ -370,7 +370,7 @@ defm MMX_PMADDWD : MMXI_binop_rm_int<0xF
defm MMX_PMADDUBSW : SS3I_binop_rm_int_mm<0x04, "pmaddubsw",
int_x86_ssse3_pmadd_ub_sw,
SchedWriteVecIMul.MMX>;
-let Predicates = [HasSSE1] in {
+let Predicates = [HasMMX, HasSSE1] in {
defm MMX_PAVGB : MMXI_binop_rm_int<0xE0, "pavgb", int_x86_mmx_pavg_b,
SchedWriteVecALU.MMX, 1>;
defm MMX_PAVGW : MMXI_binop_rm_int<0xE3, "pavgw", int_x86_mmx_pavg_w,
@@ -534,7 +534,7 @@ let Constraints = "$src1 = $dst" in {
}
// Extract / Insert
-let Predicates = [HasSSE1] in
+let Predicates = [HasMMX, HasSSE1] in
def MMX_PEXTRWrr: MMXIi8<0xC5, MRMSrcReg,
(outs GR32orGR64:$dst), (ins VR64:$src1, i32u8imm:$src2),
"pextrw\t{$src2, $src1, $dst|$dst, $src1, $src2}",
@@ -542,7 +542,7 @@ def MMX_PEXTRWrr: MMXIi8<0xC5, MRMSrcReg
imm:$src2))]>,
Sched<[WriteVecExtract]>;
let Constraints = "$src1 = $dst" in {
-let Predicates = [HasSSE1] in {
+let Predicates = [HasMMX, HasSSE1] in {
def MMX_PINSRWrr : MMXIi8<0xC4, MRMSrcReg,
(outs VR64:$dst),
(ins VR64:$src1, GR32orGR64:$src2, i32u8imm:$src3),
@@ -563,7 +563,7 @@ let Predicates = [HasSSE1] in {
}
// Mask creation
-let Predicates = [HasSSE1] in
+let Predicates = [HasMMX, HasSSE1] in
def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
(ins VR64:$src),
"pmovmskb\t{$src, $dst|$dst, $src}",
@@ -583,18 +583,18 @@ def : Pat<(x86mmx (MMX_X86movdq2q (loadv
// Misc.
let SchedRW = [SchedWriteShuffle.MMX] in {
-let Uses = [EDI], Predicates = [HasSSE1,Not64BitMode] in
+let Uses = [EDI], Predicates = [HasMMX, HasSSE1,Not64BitMode] in
def MMX_MASKMOVQ : MMXI32<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
"maskmovq\t{$mask, $src|$src, $mask}",
[(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, EDI)]>;
-let Uses = [RDI], Predicates = [HasSSE1,In64BitMode] in
+let Uses = [RDI], Predicates = [HasMMX, HasSSE1,In64BitMode] in
def MMX_MASKMOVQ64: MMXI64<0xF7, MRMSrcReg, (outs), (ins VR64:$src, VR64:$mask),
"maskmovq\t{$mask, $src|$src, $mask}",
[(int_x86_mmx_maskmovq VR64:$src, VR64:$mask, RDI)]>;
}
// 64-bit bit convert.
-let Predicates = [HasSSE2] in {
+let Predicates = [HasMMX, HasSSE2] in {
def : Pat<(f64 (bitconvert (x86mmx VR64:$src))),
(MMX_MOVQ2FR64rr VR64:$src)>;
def : Pat<(x86mmx (bitconvert (f64 FR64:$src))),
Modified: llvm/trunk/test/CodeGen/X86/pr23246.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/pr23246.ll?rev=333984&r1=333983&r2=333984&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/pr23246.ll (original)
+++ llvm/trunk/test/CodeGen/X86/pr23246.ll Mon Jun 4 23:20:06 2018
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple x86_64-unknown-unknown | FileCheck %s
+; RUN: llc < %s -mtriple x86_64-unknown-unknown -mattr=mmx | FileCheck %s
target datalayout = "e-m:o-i64:64-f80:128-n8:16:32:64-S128"
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