[PATCH] D47690: [X86][BMI][TBM] Only demand bottom 16-bits of the BEXTR control op (PR34042)

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: lib/Target/X86/X86InstrCompiler.td:2047
-            (BEXTRI32ri GR32:$src1, imm:$src2)>;
   def : Pat<(X86bextr (loadi32 addr:$src1), (i32 imm:$src2)),
             (BEXTRI32mi addr:$src1, imm:$src2)>;
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Why aren't these load patterns redundant now?


Repository:
  rL LLVM

https://reviews.llvm.org/D47690