[llvm] r333838 - Remove SETCCE use from Lanai's backend
Amaury Sechet via llvm-commits
llvm-commits at lists.llvm.org
Sun Jun 3 05:56:25 PDT 2018
Author: deadalnix
Date: Sun Jun 3 05:56:24 2018
New Revision: 333838
URL: http://llvm.org/viewvc/llvm-project?rev=333838&view=rev
Log:
Remove SETCCE use from Lanai's backend
Summary: This creates a small perf regression, but after talking with Jacques Pienaar, he was good with it to get things moving toward removng SETCCE.
Reviewers: jpienaar, bryant
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D47626
Modified:
llvm/trunk/lib/Target/Lanai/LanaiISelLowering.cpp
llvm/trunk/lib/Target/Lanai/LanaiISelLowering.h
llvm/trunk/test/CodeGen/Lanai/comparisons_i64.ll
Modified: llvm/trunk/lib/Target/Lanai/LanaiISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiISelLowering.cpp?rev=333838&r1=333837&r2=333838&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiISelLowering.cpp Sun Jun 3 05:56:24 2018
@@ -87,7 +87,6 @@ LanaiTargetLowering::LanaiTargetLowering
setOperationAction(ISD::BR_JT, MVT::Other, Expand);
setOperationAction(ISD::BRCOND, MVT::Other, Expand);
setOperationAction(ISD::SETCC, MVT::i32, Custom);
- setOperationAction(ISD::SETCCE, MVT::i32, Custom);
setOperationAction(ISD::SELECT, MVT::i32, Expand);
setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
@@ -193,8 +192,6 @@ SDValue LanaiTargetLowering::LowerOperat
return LowerSELECT_CC(Op, DAG);
case ISD::SETCC:
return LowerSETCC(Op, DAG);
- case ISD::SETCCE:
- return LowerSETCCE(Op, DAG);
case ISD::SHL_PARTS:
return LowerSHL_PARTS(Op, DAG);
case ISD::SRL_PARTS:
@@ -969,19 +966,6 @@ SDValue LanaiTargetLowering::LowerMUL(SD
return Res;
}
-SDValue LanaiTargetLowering::LowerSETCCE(SDValue Op, SelectionDAG &DAG) const {
- SDValue LHS = Op.getOperand(0);
- SDValue RHS = Op.getOperand(1);
- SDValue Carry = Op.getOperand(2);
- SDValue Cond = Op.getOperand(3);
- SDLoc DL(Op);
-
- LPCC::CondCode CC = IntCondCCodeToICC(Cond, DL, RHS, DAG);
- SDValue TargetCC = DAG.getConstant(CC, DL, MVT::i32);
- SDValue Flag = DAG.getNode(LanaiISD::SUBBF, DL, MVT::Glue, LHS, RHS, Carry);
- return DAG.getNode(LanaiISD::SETCC, DL, Op.getValueType(), TargetCC, Flag);
-}
-
SDValue LanaiTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
SDValue LHS = Op.getOperand(0);
SDValue RHS = Op.getOperand(1);
Modified: llvm/trunk/lib/Target/Lanai/LanaiISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiISelLowering.h?rev=333838&r1=333837&r2=333838&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiISelLowering.h (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiISelLowering.h Sun Jun 3 05:56:24 2018
@@ -87,7 +87,6 @@ public:
SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
- SDValue LowerSETCCE(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
Modified: llvm/trunk/test/CodeGen/Lanai/comparisons_i64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Lanai/comparisons_i64.ll?rev=333838&r1=333837&r2=333838&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Lanai/comparisons_i64.ll (original)
+++ llvm/trunk/test/CodeGen/Lanai/comparisons_i64.ll Sun Jun 3 05:56:24 2018
@@ -28,9 +28,12 @@ define i32 @ne_i64(i64 inreg %x, i64 inr
}
; CHECK-LABEL: slt_i64:
-; CHECK: sub.f %r7, %r19, %r3
-; CHECK: subb.f %r6, %r18, %r3
-; CHECK-NEXT: slt
+; CHECK: sub.f %r6, %r18, %r0
+; CHECK-NEXT: slt %r3
+; CHECK-NEXT: sub.f %r7, %r19, %r0
+; CHECK-NEXT: sult %r9
+; CHECK-NEXT: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sel.eq %r9, %r3, %rv
define i32 @slt_i64(i64 inreg %x, i64 inreg %y) {
%a = icmp slt i64 %x, %y
%b = zext i1 %a to i32
@@ -38,9 +41,12 @@ define i32 @slt_i64(i64 inreg %x, i64 in
}
; CHECK-LABEL: sle_i64:
-; CHECK: sub.f %r19, %r7, %r3
-; CHECK: subb.f %r18, %r6, %r3
-; CHECK-NEXT: sge %rv
+; CHECK: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sle %r3
+; CHECK-NEXT: sub.f %r7, %r19, %r0
+; CHECK-NEXT: sule %r9
+; CHECK-NEXT: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sel.eq %r9, %r3, %rv
define i32 @sle_i64(i64 inreg %x, i64 inreg %y) {
%a = icmp sle i64 %x, %y
%b = zext i1 %a to i32
@@ -48,9 +54,12 @@ define i32 @sle_i64(i64 inreg %x, i64 in
}
; CHECK-LABEL: ult_i64:
-; CHECK: sub.f %r7, %r19, %r3
-; CHECK: subb.f %r6, %r18, %r3
-; CHECK-NEXT: sult %rv
+; CHECK: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sult %r3
+; CHECK-NEXT: sub.f %r7, %r19, %r0
+; CHECK-NEXT: sult %r9
+; CHECK-NEXT: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sel.eq %r9, %r3, %rv
define i32 @ult_i64(i64 inreg %x, i64 inreg %y) {
%a = icmp ult i64 %x, %y
%b = zext i1 %a to i32
@@ -58,9 +67,12 @@ define i32 @ult_i64(i64 inreg %x, i64 in
}
; CHECK-LABEL: ule_i64:
-; CHECK: sub.f %r19, %r7, %r3
-; CHECK: subb.f %r18, %r6, %r3
-; CHECK-NEXT: suge %rv
+; CHECK: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sule %r3
+; CHECK-NEXT: sub.f %r7, %r19, %r0
+; CHECK-NEXT: sule %r9
+; CHECK-NEXT: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sel.eq %r9, %r3, %rv
define i32 @ule_i64(i64 inreg %x, i64 inreg %y) {
%a = icmp ule i64 %x, %y
%b = zext i1 %a to i32
@@ -68,9 +80,12 @@ define i32 @ule_i64(i64 inreg %x, i64 in
}
; CHECK-LABEL: sgt_i64:
-; CHECK: sub.f %r19, %r7, %r3
-; CHECK: subb.f %r18, %r6, %r3
-; CHECK-NEXT: slt %rv
+; CHECK: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sgt %r3
+; CHECK-NEXT: sub.f %r7, %r19, %r0
+; CHECK-NEXT: sugt %r9
+; CHECK-NEXT: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sel.eq %r9, %r3, %rv
define i32 @sgt_i64(i64 inreg %x, i64 inreg %y) {
%a = icmp sgt i64 %x, %y
%b = zext i1 %a to i32
@@ -78,9 +93,12 @@ define i32 @sgt_i64(i64 inreg %x, i64 in
}
; CHECK-LABEL: sge_i64:
-; CHECK: sub.f %r7, %r19, %r3
-; CHECK: subb.f %r6, %r18, %r3
-; CHECK-NEXT: sge %rv
+; CHECK: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sge %r3
+; CHECK-NEXT: sub.f %r7, %r19, %r0
+; CHECK-NEXT: suge %r9
+; CHECK-NEXT: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sel.eq %r9, %r3, %rv
define i32 @sge_i64(i64 inreg %x, i64 inreg %y) {
%a = icmp sge i64 %x, %y
%b = zext i1 %a to i32
@@ -88,9 +106,12 @@ define i32 @sge_i64(i64 inreg %x, i64 in
}
; CHECK-LABEL: ugt_i64:
-; CHECK: sub.f %r19, %r7, %r3
-; CHECK: subb.f %r18, %r6, %r3
-; CHECK-NEXT: sult %rv
+; CHECK: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sugt %r3
+; CHECK-NEXT: sub.f %r7, %r19, %r0
+; CHECK-NEXT: sugt %r9
+; CHECK-NEXT: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sel.eq %r9, %r3, %rv
define i32 @ugt_i64(i64 inreg %x, i64 inreg %y) {
%a = icmp ugt i64 %x, %y
%b = zext i1 %a to i32
@@ -98,9 +119,12 @@ define i32 @ugt_i64(i64 inreg %x, i64 in
}
; CHECK-LABEL: uge_i64:
-; CHECK: sub.f %r7, %r19, %r3
-; CHECK: subb.f %r6, %r18, %r3
-; CHECK-NEXT: suge %rv
+; CHECK: sub.f %r6, %r18, %r0
+; CHECK-NEXT: suge %r3
+; CHECK-NEXT: sub.f %r7, %r19, %r0
+; CHECK-NEXT: suge %r9
+; CHECK-NEXT: sub.f %r6, %r18, %r0
+; CHECK-NEXT: sel.eq %r9, %r3, %rv
define i32 @uge_i64(i64 inreg %x, i64 inreg %y) {
%a = icmp uge i64 %x, %y
%b = zext i1 %a to i32
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