[llvm] r333827 - [X86][BMI2] Test i32 intrinsics on 32/64 bits + branch off i64 tests

Simon Pilgrim via llvm-commits llvm-commits at lists.llvm.org
Sat Jun 2 10:22:13 PDT 2018


Author: rksimon
Date: Sat Jun  2 10:22:13 2018
New Revision: 333827

URL: http://llvm.org/viewvc/llvm-project?rev=333827&view=rev
Log:
[X86][BMI2] Test i32 intrinsics on 32/64 bits + branch off i64 tests

I had to tweak the i32 tests so we check both reg-reg and reg-mem cases.

I also added i64 load tests.

Part of ongoing work to ensure we test all intrinsic style tests on 32 and 64 bit targets where possible.

Added:
    llvm/trunk/test/CodeGen/X86/bmi2-x86_64.ll
Modified:
    llvm/trunk/test/CodeGen/X86/bmi2.ll

Added: llvm/trunk/test/CodeGen/X86/bmi2-x86_64.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi2-x86_64.ll?rev=333827&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bmi2-x86_64.ll (added)
+++ llvm/trunk/test/CodeGen/X86/bmi2-x86_64.ll Sat Jun  2 10:22:13 2018
@@ -0,0 +1,102 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi,+bmi2 | FileCheck %s --check-prefixes=CHECK
+
+define i64 @bzhi64(i64 %x, i64 %y)   {
+; CHECK-LABEL: bzhi64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    bzhiq %rsi, %rdi, %rax
+; CHECK-NEXT:    retq
+  %tmp = tail call i64 @llvm.x86.bmi.bzhi.64(i64 %x, i64 %y)
+  ret i64 %tmp
+}
+
+define i64 @bzhi64_load(i64* %x, i64 %y)   {
+; CHECK-LABEL: bzhi64_load:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    bzhiq %rsi, (%rdi), %rax
+; CHECK-NEXT:    retq
+  %x1 = load i64, i64* %x
+  %tmp = tail call i64 @llvm.x86.bmi.bzhi.64(i64 %x1, i64 %y)
+  ret i64 %tmp
+}
+
+declare i64 @llvm.x86.bmi.bzhi.64(i64, i64)
+
+define i64 @pdep64(i64 %x, i64 %y)   {
+; CHECK-LABEL: pdep64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pdepq %rsi, %rdi, %rax
+; CHECK-NEXT:    retq
+  %tmp = tail call i64 @llvm.x86.bmi.pdep.64(i64 %x, i64 %y)
+  ret i64 %tmp
+}
+
+define i64 @pdep64_load(i64 %x, i64* %y)   {
+; CHECK-LABEL: pdep64_load:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pdepq (%rsi), %rdi, %rax
+; CHECK-NEXT:    retq
+  %y1 = load i64, i64* %y
+  %tmp = tail call i64 @llvm.x86.bmi.pdep.64(i64 %x, i64 %y1)
+  ret i64 %tmp
+}
+
+declare i64 @llvm.x86.bmi.pdep.64(i64, i64)
+
+define i64 @pext64(i64 %x, i64 %y)   {
+; CHECK-LABEL: pext64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pextq %rsi, %rdi, %rax
+; CHECK-NEXT:    retq
+  %tmp = tail call i64 @llvm.x86.bmi.pext.64(i64 %x, i64 %y)
+  ret i64 %tmp
+}
+
+define i64 @pext64_load(i64 %x, i64* %y)   {
+; CHECK-LABEL: pext64_load:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pextq (%rsi), %rdi, %rax
+; CHECK-NEXT:    retq
+  %y1 = load i64, i64* %y
+  %tmp = tail call i64 @llvm.x86.bmi.pext.64(i64 %x, i64 %y1)
+  ret i64 %tmp
+}
+
+declare i64 @llvm.x86.bmi.pext.64(i64, i64)
+
+define i64 @mulx64(i64 %x, i64 %y, i64* %p)   {
+; CHECK-LABEL: mulx64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq %rdx, %rcx
+; CHECK-NEXT:    movq %rdi, %rdx
+; CHECK-NEXT:    mulxq %rsi, %rax, %rdx
+; CHECK-NEXT:    movq %rdx, (%rcx)
+; CHECK-NEXT:    retq
+  %x1 = zext i64 %x to i128
+  %y1 = zext i64 %y to i128
+  %r1 = mul i128 %x1, %y1
+  %h1 = lshr i128 %r1, 64
+  %h  = trunc i128 %h1 to i64
+  %l  = trunc i128 %r1 to i64
+  store i64 %h, i64* %p
+  ret i64 %l
+}
+
+define i64 @mulx64_load(i64 %x, i64* %y, i64* %p)   {
+; CHECK-LABEL: mulx64_load:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq %rdx, %rcx
+; CHECK-NEXT:    movq %rdi, %rdx
+; CHECK-NEXT:    mulxq (%rsi), %rax, %rdx
+; CHECK-NEXT:    movq %rdx, (%rcx)
+; CHECK-NEXT:    retq
+  %y1 = load i64, i64* %y
+  %x2 = zext i64 %x to i128
+  %y2 = zext i64 %y1 to i128
+  %r1 = mul i128 %x2, %y2
+  %h1 = lshr i128 %r1, 64
+  %h  = trunc i128 %h1 to i64
+  %l  = trunc i128 %r1 to i64
+  store i64 %h, i64* %p
+  ret i64 %l
+}

Modified: llvm/trunk/test/CodeGen/X86/bmi2.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/bmi2.ll?rev=333827&r1=333826&r2=333827&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/bmi2.ll (original)
+++ llvm/trunk/test/CodeGen/X86/bmi2.ll Sat Jun  2 10:22:13 2018
@@ -1,20 +1,38 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi,+bmi2 | FileCheck %s
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+bmi,+bmi2 | FileCheck %s --check-prefixes=CHECK,X86
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi,+bmi2 | FileCheck %s --check-prefixes=CHECK,X64
 
 define i32 @bzhi32(i32 %x, i32 %y)   {
-; CHECK-LABEL: bzhi32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    bzhil %esi, %edi, %eax
-; CHECK-NEXT:    retq
-  %tmp = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %x, i32 %y)
+; X86-LABEL: bzhi32:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT:    addl %ecx, %ecx
+; X86-NEXT:    bzhil %eax, %ecx, %eax
+; X86-NEXT:    retl
+;
+; X64-LABEL: bzhi32:
+; X64:       # %bb.0:
+; X64-NEXT:    addl %edi, %edi
+; X64-NEXT:    bzhil %esi, %edi, %eax
+; X64-NEXT:    retq
+  %x1 = add i32 %x, %x
+  %tmp = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %x1, i32 %y)
   ret i32 %tmp
 }
 
 define i32 @bzhi32_load(i32* %x, i32 %y)   {
-; CHECK-LABEL: bzhi32_load:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    bzhil %esi, (%rdi), %eax
-; CHECK-NEXT:    retq
+; X86-LABEL: bzhi32_load:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT:    bzhil %eax, (%ecx), %eax
+; X86-NEXT:    retl
+;
+; X64-LABEL: bzhi32_load:
+; X64:       # %bb.0:
+; X64-NEXT:    bzhil %esi, (%rdi), %eax
+; X64-NEXT:    retq
   %x1 = load i32, i32* %x
   %tmp = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %x1, i32 %y)
   ret i32 %tmp
@@ -22,31 +40,37 @@ define i32 @bzhi32_load(i32* %x, i32 %y)
 
 declare i32 @llvm.x86.bmi.bzhi.32(i32, i32)
 
-define i64 @bzhi64(i64 %x, i64 %y)   {
-; CHECK-LABEL: bzhi64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    bzhiq %rsi, %rdi, %rax
-; CHECK-NEXT:    retq
-  %tmp = tail call i64 @llvm.x86.bmi.bzhi.64(i64 %x, i64 %y)
-  ret i64 %tmp
-}
-
-declare i64 @llvm.x86.bmi.bzhi.64(i64, i64)
-
 define i32 @pdep32(i32 %x, i32 %y)   {
-; CHECK-LABEL: pdep32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    pdepl %esi, %edi, %eax
-; CHECK-NEXT:    retq
-  %tmp = tail call i32 @llvm.x86.bmi.pdep.32(i32 %x, i32 %y)
+; X86-LABEL: pdep32:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT:    addl %ecx, %ecx
+; X86-NEXT:    pdepl %ecx, %eax, %eax
+; X86-NEXT:    retl
+;
+; X64-LABEL: pdep32:
+; X64:       # %bb.0:
+; X64-NEXT:    addl %esi, %esi
+; X64-NEXT:    pdepl %esi, %edi, %eax
+; X64-NEXT:    retq
+  %y1 = add i32 %y, %y
+  %tmp = tail call i32 @llvm.x86.bmi.pdep.32(i32 %x, i32 %y1)
   ret i32 %tmp
 }
 
 define i32 @pdep32_load(i32 %x, i32* %y)   {
-; CHECK-LABEL: pdep32_load:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    pdepl (%rsi), %edi, %eax
-; CHECK-NEXT:    retq
+; X86-LABEL: pdep32_load:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT:    pdepl (%eax), %ecx, %eax
+; X86-NEXT:    retl
+;
+; X64-LABEL: pdep32_load:
+; X64:       # %bb.0:
+; X64-NEXT:    pdepl (%rsi), %edi, %eax
+; X64-NEXT:    retq
   %y1 = load i32, i32* %y
   %tmp = tail call i32 @llvm.x86.bmi.pdep.32(i32 %x, i32 %y1)
   ret i32 %tmp
@@ -54,31 +78,37 @@ define i32 @pdep32_load(i32 %x, i32* %y)
 
 declare i32 @llvm.x86.bmi.pdep.32(i32, i32)
 
-define i64 @pdep64(i64 %x, i64 %y)   {
-; CHECK-LABEL: pdep64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    pdepq %rsi, %rdi, %rax
-; CHECK-NEXT:    retq
-  %tmp = tail call i64 @llvm.x86.bmi.pdep.64(i64 %x, i64 %y)
-  ret i64 %tmp
-}
-
-declare i64 @llvm.x86.bmi.pdep.64(i64, i64)
-
 define i32 @pext32(i32 %x, i32 %y)   {
-; CHECK-LABEL: pext32:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    pextl %esi, %edi, %eax
-; CHECK-NEXT:    retq
-  %tmp = tail call i32 @llvm.x86.bmi.pext.32(i32 %x, i32 %y)
+; X86-LABEL: pext32:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT:    addl %ecx, %ecx
+; X86-NEXT:    pextl %ecx, %eax, %eax
+; X86-NEXT:    retl
+;
+; X64-LABEL: pext32:
+; X64:       # %bb.0:
+; X64-NEXT:    addl %esi, %esi
+; X64-NEXT:    pextl %esi, %edi, %eax
+; X64-NEXT:    retq
+  %y1 = add i32 %y, %y
+  %tmp = tail call i32 @llvm.x86.bmi.pext.32(i32 %x, i32 %y1)
   ret i32 %tmp
 }
 
 define i32 @pext32_load(i32 %x, i32* %y)   {
-; CHECK-LABEL: pext32_load:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    pextl (%rsi), %edi, %eax
-; CHECK-NEXT:    retq
+; X86-LABEL: pext32_load:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT:    pextl (%eax), %ecx, %eax
+; X86-NEXT:    retl
+;
+; X64-LABEL: pext32_load:
+; X64:       # %bb.0:
+; X64-NEXT:    pextl (%rsi), %edi, %eax
+; X64-NEXT:    retq
   %y1 = load i32, i32* %y
   %tmp = tail call i32 @llvm.x86.bmi.pext.32(i32 %x, i32 %y1)
   ret i32 %tmp
@@ -86,14 +116,72 @@ define i32 @pext32_load(i32 %x, i32* %y)
 
 declare i32 @llvm.x86.bmi.pext.32(i32, i32)
 
-define i64 @pext64(i64 %x, i64 %y)   {
-; CHECK-LABEL: pext64:
-; CHECK:       # %bb.0:
-; CHECK-NEXT:    pextq %rsi, %rdi, %rax
-; CHECK-NEXT:    retq
-  %tmp = tail call i64 @llvm.x86.bmi.pext.64(i64 %x, i64 %y)
-  ret i64 %tmp
+define i32 @mulx32(i32 %x, i32 %y, i32* %p)   {
+; X86-LABEL: mulx32:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT:    addl %edx, %edx
+; X86-NEXT:    addl %eax, %eax
+; X86-NEXT:    mulxl %eax, %eax, %edx
+; X86-NEXT:    movl %edx, (%ecx)
+; X86-NEXT:    retl
+;
+; X64-LABEL: mulx32:
+; X64:       # %bb.0:
+; X64-NEXT:    # kill: def $esi killed $esi def $rsi
+; X64-NEXT:    # kill: def $edi killed $edi def $rdi
+; X64-NEXT:    addl %edi, %edi
+; X64-NEXT:    addl %esi, %esi
+; X64-NEXT:    imulq %rdi, %rsi
+; X64-NEXT:    movq %rsi, %rax
+; X64-NEXT:    shrq $32, %rax
+; X64-NEXT:    movl %eax, (%rdx)
+; X64-NEXT:    movl %esi, %eax
+; X64-NEXT:    retq
+  %x1 = add i32 %x, %x
+  %y1 = add i32 %y, %y
+  %x2 = zext i32 %x1 to i64
+  %y2 = zext i32 %y1 to i64
+  %r1 = mul i64 %x2, %y2
+  %h1 = lshr i64 %r1, 32
+  %h  = trunc i64 %h1 to i32
+  %l  = trunc i64 %r1 to i32
+  store i32 %h, i32* %p
+  ret i32 %l
+}
+
+define i32 @mulx32_load(i32 %x, i32* %y, i32* %p)   {
+; X86-LABEL: mulx32_load:
+; X86:       # %bb.0:
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; X86-NEXT:    addl %edx, %edx
+; X86-NEXT:    mulxl (%eax), %eax, %edx
+; X86-NEXT:    movl %edx, (%ecx)
+; X86-NEXT:    retl
+;
+; X64-LABEL: mulx32_load:
+; X64:       # %bb.0:
+; X64-NEXT:    # kill: def $edi killed $edi def $rdi
+; X64-NEXT:    addl %edi, %edi
+; X64-NEXT:    movl (%rsi), %eax
+; X64-NEXT:    imulq %rax, %rdi
+; X64-NEXT:    movq %rdi, %rax
+; X64-NEXT:    shrq $32, %rax
+; X64-NEXT:    movl %eax, (%rdx)
+; X64-NEXT:    movl %edi, %eax
+; X64-NEXT:    retq
+  %x1 = add i32 %x, %x
+  %y1 = load i32, i32* %y
+  %x2 = zext i32 %x1 to i64
+  %y2 = zext i32 %y1 to i64
+  %r1 = mul i64 %x2, %y2
+  %h1 = lshr i64 %r1, 32
+  %h  = trunc i64 %h1 to i32
+  %l  = trunc i64 %r1 to i32
+  store i32 %h, i32* %p
+  ret i32 %l
 }
-
-declare i64 @llvm.x86.bmi.pext.64(i64, i64)
-




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