[PATCH] D47589: [RISCV] Add codegen support for atomic load/stores with RV32A

[JF Bastien via Phabricator via llvm-commits]

jfb added a subscriber: t.p.northover.
jfb added a comment.

In https://reviews.llvm.org/D47589#1119145, @jyknight wrote:

> In https://reviews.llvm.org/D47589#1118174, @jfb wrote:
>
> > In https://reviews.llvm.org/D47589#1118128, @efriedma wrote:
> >
> > > The compiler-rt "__atomic_*" are known to be buggy; see https://reviews.llvm.org/D45321
> >
> >
> > Seems you're advocating that this patch (and the LangRef) follow the reality you'd like to have, not the one we actually have :-)
> >  So I'll re-iterate: is the alignment check a documented guarantee that `__atomic_*` functions **must** provide, in all of their implementations?
>
>
> The compiler must not emit a call to the `__atomic_load_4`  (and other names with sizes on the end) functions on unaligned memory -- that function can assume its argument is aligned.
>
> But `__atomic_load` (size is given as an argument) must be safe to call on both aligned and unaligned memory, *and* must safely interoperate both with `__atomic_load_4` and inline-emitted atomics if the current hardware supports them.


Can you refer to documentation that says so? I'm happy if that's the case, but I want to be really sure it is. Not just for compiler-rt, but for GCC as well (I've ping'd someone on that side to get more info). If so the @t.p.northover's patch fixing some alignment stuff is also something we want, and we'll want to update some documentation.


https://reviews.llvm.org/D47589