[PATCH] D47425: [AArch64][GlobalISel] Zero-extend s1 values when returning.

[Amara Emerson via Phabricator via llvm-commits]

aemerson added inline comments.


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Comment at: lib/Target/AArch64/AArch64CallLowering.cpp:224
 bool AArch64CallLowering::lowerReturn(MachineIRBuilder &MIRBuilder,
                                       const Value *Val, unsigned VReg) const {
   MachineFunction &MF = MIRBuilder.getMF();
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efriedma wrote:
> Do you also need to modify argument passing, to handle something like `void a(void x(_Bool)) { x(1); }`?
That looks to work already, we zero extend for that case:

```
    %0:_(p0) = COPY $x0
    %3:_(s1) = G_CONSTANT i1 true
    %1:_(p0) = G_FRAME_INDEX %stack.0.x.addr
    G_STORE %0(p0), %1(p0) :: (store 8 into %ir.x.addr)
    %2:gpr64(p0) = G_LOAD %1(p0) :: (load 8 from %ir.x.addr)
    ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
    %4:_(s32) = G_ZEXT %3(s1)
    $w0 = COPY %4(s32)
    BLR %2(p0), csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0
    ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
    RET_ReallyLR
```


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Comment at: lib/Target/AArch64/AArch64CallLowering.cpp:237
+      MIRBuilder.buildZExt(ZExt, VReg);
+      VReg = ZExt;
+    }
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aditya_nandakumar wrote:
> rtereshin wrote:
> > I think the preferred way of doing this would be `VReg = MIRBuilder.buildZExt(LLT::scalar(8), VReg)->getOperand(0).getReg();` just to avoid the explicit `MachineRegisterInfo::createGenericVirtualRegister` call. + at aditya_nandakumar 
> That would be my preference as well.
Will do, thanks.


Repository:
  rL LLVM

https://reviews.llvm.org/D47425