[PATCH] D47583: [mips] Guard 'nop' properly and add mips16's nop instruction

[Simon Dardis via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL333739: [mips] Guard 'nop' properly and add mips16's nop instruction (authored by sdardis, committed by ).

Repository:
  rL LLVM

https://reviews.llvm.org/D47583

Files:
  llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
  llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
  llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
  llvm/trunk/test/MC/Mips/mips16/invalid.s
  llvm/trunk/test/MC/Mips/mips16/valid.s


Index: llvm/trunk/test/MC/Mips/mips16/invalid.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips16/invalid.s
+++ llvm/trunk/test/MC/Mips/mips16/invalid.s
@@ -0,0 +1,10 @@
+# RUN: not llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mips16 < %s 2> %t
+# RUN: FileCheck %s < %t
+
+# Instructions which are invalid.
+
+$label:
+  nop 4         # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
+  nop $4        # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
+  nop $label    # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
+
Index: llvm/trunk/test/MC/Mips/mips16/valid.s
===================================================================
--- llvm/trunk/test/MC/Mips/mips16/valid.s
+++ llvm/trunk/test/MC/Mips/mips16/valid.s
@@ -0,0 +1,3 @@
+# RUN: llvm-mc -arch=mips -mcpu=mips32r2 -mattr=+mips16 -show-encoding -show-inst < %s
+
+  nop
Index: llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
+++ llvm/trunk/lib/Target/Mips/Mips16InstrInfo.td
@@ -1914,3 +1914,7 @@
 MipsPseudo16<(outs), (ins cpinst_operand:$instid, cpinst_operand:$cpidx,
                       i32imm:$size), "foo", []>;
 
+// Instruction Aliases
+
+let EncodingPredicates = [InMips16Mode] in
+def : MipsInstAlias<"nop", (Move32R16 ZERO, S0)>;
Index: llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
+++ llvm/trunk/lib/Target/Mips/MipsInstrInfo.td
@@ -2308,17 +2308,19 @@
   /// Word Swap Bytes Within Halfwords
   def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>, SEB_FM<2, 0x20>,
              ISA_MIPS32R2;
-}
 
-/// No operation.
-def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
+  /// No operation.
+  def NOP : PseudoSE<(outs), (ins), []>,
+                     PseudoInstExpansion<(SLL ZERO, ZERO, 0)>, ISA_MIPS1;
+
+  // FrameIndexes are legalized when they are operands from load/store
+  // instructions. The same not happens for stack address copies, so an
+  // add op with mem ComplexPattern is used and the stack address copy
+  // can be matched. It's similar to Sparc LEA_ADDRi
+  let AdditionalPredicates = [NotInMicroMips] in
+    def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>, ISA_MIPS1;
 
-// FrameIndexes are legalized when they are operands from load/store
-// instructions. The same not happens for stack address copies, so an
-// add op with mem ComplexPattern is used and the stack address copy
-// can be matched. It's similar to Sparc LEA_ADDRi
-let AdditionalPredicates = [NotInMicroMips] in
-  def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>, ISA_MIPS1;
+}
 
 // MADD*/MSUB*
 def MADD  : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
@@ -2636,7 +2638,8 @@
   def : MipsInstAlias<
           "not $rt",
           (NOR GPR32Opnd:$rt, GPR32Opnd:$rt, ZERO), 0>;
-  def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
+
+  def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>, ISA_MIPS1;
 
   defm : OneOrTwoOperandMacroImmediateAlias<"add", ADDi>, ISA_MIPS1_NOT_32R6_64R6;
 
Index: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
===================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
@@ -1278,8 +1278,8 @@
                                      II_DIVU, 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
 
   def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>, ISA_MICROMIPS;
-  def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>;
-  def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>;
+  def : MipsInstAlias<"nop", (SLL_MM ZERO, ZERO, 0), 1>, ISA_MICROMIPS;
+  def : MipsInstAlias<"nop", (MOVE16_MM ZERO, ZERO), 1>, ISA_MICROMIPS;
   def : MipsInstAlias<"ei", (EI_MM ZERO), 1>, ISA_MICROMIPS;
   def : MipsInstAlias<"di", (DI_MM ZERO), 1>, ISA_MICROMIPS;
   def : MipsInstAlias<"neg $rt, $rs",


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