[llvm] r333717 - [X86] Make sure the check for VEX.vvvv being all ones on instructions that don't use it doesn't ignore a bit in 32-bit mode.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Thu May 31 18:23:52 2018
New Revision: 333717

URL: http://llvm.org/viewvc/llvm-project?rev=333717&view=rev
Log:
[X86] Make sure the check for VEX.vvvv being all ones on instructions that don't use it doesn't ignore a bit in 32-bit mode.

Added:
    llvm/trunk/test/MC/Disassembler/X86/invalid-VEX-vvvv-32.txt
Modified:
    llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp

Modified: llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp?rev=333717&r1=333716&r2=333717&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp (original)
+++ llvm/trunk/lib/Target/X86/Disassembler/X86DisassemblerDecoder.cpp Thu May 31 18:23:52 2018
@@ -1695,7 +1695,7 @@ static int readVVVV(struct InternalInstr
     return -1;
 
   if (insn->mode != MODE_64BIT)
-    vvvv &= 0x7;
+    vvvv &= 0xf; // Can only clear bit 4. Bit 3 must be cleared later.
 
   insn->vvvv = static_cast<Reg>(vvvv);
   return 0;
@@ -1860,6 +1860,8 @@ static int readOperands(struct InternalI
       needVVVV = 0; /* Mark that we have found a VVVV operand. */
       if (!hasVVVV)
         return -1;
+      if (insn->mode != MODE_64BIT)
+        insn->vvvv = static_cast<Reg>(insn->vvvv & 0x7);
       if (fixupReg(insn, &Op))
         return -1;
       break;

Added: llvm/trunk/test/MC/Disassembler/X86/invalid-VEX-vvvv-32.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/X86/invalid-VEX-vvvv-32.txt?rev=333717&view=auto
==============================================================================
--- llvm/trunk/test/MC/Disassembler/X86/invalid-VEX-vvvv-32.txt (added)
+++ llvm/trunk/test/MC/Disassembler/X86/invalid-VEX-vvvv-32.txt Thu May 31 18:23:52 2018
@@ -0,0 +1,4 @@
+# RUN: llvm-mc --disassemble %s -triple=i686-apple-darwin9 2>&1 | grep "invalid instruction encoding"
+
+# Make sure the VEX.vvvv being all 1s check doesn't ignore bit 3 in 32-bit mode.
+0xc4 0xe1 0xb9 0x7e 0xc0