[PATCH] D47589: [RISCV] Add codegen support for atomic load/stores with RV32A

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

> Say I have two TUs which share an atomic location, but have a different idea of its alignment. They both access that location, one with libcall and one with an instruction. That's clearly broken. Can this happen?

No, it's not broken (assuming the location is actually aligned at runtime). In the translation unit where the location is known aligned, it'll use the native lock-free instruction.  In the other translation unit, the libatomic call will check the alignment of the address at runtime, see it's aligned, and use a compatible lock-free implementation.


https://reviews.llvm.org/D47589