[PATCH] D47587: [RISCV] Codegen support for atomic operations on RV32I

[JF Bastien via Phabricator via llvm-commits]

jfb added a comment.

Looks fine in general, though I know ~nothing of RISCV.



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Comment at: lib/Target/RISCV/RISCVISelLowering.cpp:145
 
+  setMaxAtomicSizeInBitsSupported(0);
+
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Will you always want libcalls, or is it just a temporary thing. Seems you want a comment to explain.


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Comment at: test/CodeGen/RISCV/atomic-fence.ll:27
+; RV32I-NEXT:    fence rw, rw
+; RV32I-NEXT:    ret
+  fence acq_rel
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You should comment about fence.tso here as well.


https://reviews.llvm.org/D47587