[llvm] r333536 - [mips] Sink PredicateControl further down the class hierarchy.
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Wed May 30 05:40:53 PDT 2018
Author: sdardis
Date: Wed May 30 05:40:53 2018
New Revision: 333536
URL: http://llvm.org/viewvc/llvm-project?rev=333536&view=rev
Log:
[mips] Sink PredicateControl further down the class hierarchy.
Previously PredicateControl in some cases was a member of <X>Inst classes
for some X (DSP, EVA) or was in more irregular place in the hierarchry
for any given instruction.
This patch moves PredicateControl down to the root so that it is consistently
available. Then correct the base class of microMIPS instructions as using
EncodingPredicates instead of the general Predicates field of Instruction.
Reviewers: smaksimovic, abeserminji, atanasyan
Differential Revision: https://reviews.llvm.org/D47526
Modified:
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td
llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrFormats.td
llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td
llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td
llvm/trunk/lib/Target/Mips/MipsDSPInstrFormats.td
llvm/trunk/lib/Target/Mips/MipsEVAInstrFormats.td
llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td
llvm/trunk/lib/Target/Mips/MipsMTInstrFormats.td
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td?rev=333536&r1=333535&r2=333536&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrFormats.td Wed May 30 05:40:53 2018
@@ -17,13 +17,6 @@ class MMR6Arch<string opstr> {
string DecoderNamespace = "MicroMipsR6";
}
-// Class used for microMIPS32r6 instructions.
-class MicroMipsR6Inst16 : PredicateControl {
- string DecoderNamespace = "MicroMipsR6";
- let InsnPredicates = [HasMips32r6];
- let EncodingPredicates = [InMicroMips];
-}
-
//===----------------------------------------------------------------------===//
//
// Disambiguators
@@ -51,7 +44,7 @@ class BC16_FM_MM16R6 {
let Inst{9-0} = offset;
}
-class BEQZC_BNEZC_FM_MM16R6<bits<6> op> : MicroMipsR6Inst16 {
+class BEQZC_BNEZC_FM_MM16R6<bits<6> op> {
bits<3> rs;
bits<7> offset;
@@ -699,7 +692,7 @@ class POOL32F_MATH_FM_MMR6<string instr_
let Inst{5-0} = 0b111011;
}
-class POOL16A_ADDU16_FM_MMR6 : MicroMipsR6Inst16 {
+class POOL16A_ADDU16_FM_MMR6 {
bits<3> rs;
bits<3> rt;
bits<3> rd;
@@ -713,7 +706,7 @@ class POOL16A_ADDU16_FM_MMR6 : MicroMips
let Inst{0} = 0;
}
-class POOL16C_AND16_FM_MMR6 : MicroMipsR6Inst16 {
+class POOL16C_AND16_FM_MMR6 {
bits<3> rt;
bits<3> rs;
@@ -725,7 +718,7 @@ class POOL16C_AND16_FM_MMR6 : MicroMipsR
let Inst{3-0} = 0b0001;
}
-class POOL16C_NOT16_FM_MMR6 : MicroMipsR6Inst16 {
+class POOL16C_NOT16_FM_MMR6 {
bits<3> rt;
bits<3> rs;
@@ -737,7 +730,7 @@ class POOL16C_NOT16_FM_MMR6 : MicroMipsR
let Inst{3-0} = 0b0000;
}
-class POOL16C_MOVEP16_FM_MMR6 : MicroMipsR6Inst16 {
+class POOL16C_MOVEP16_FM_MMR6 {
bits<3> dst_regs;
bits<3> rt;
bits<3> rs;
@@ -752,7 +745,7 @@ class POOL16C_MOVEP16_FM_MMR6 : MicroMip
let Inst{1-0} = rs{1-0};
}
-class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> : MicroMipsR6Inst16 {
+class POOL16C_OR16_XOR16_FM_MMR6<bits<4> op> {
bits<3> rt;
bits<3> rs;
@@ -787,7 +780,8 @@ class POOL16A_SUBU16_FM_MMR6 {
let Inst{0} = 0b1;
}
-class POOL32A_WRPGPR_WSBH_FM_MMR6<bits<10> funct> : MipsR6Inst {
+class POOL32A_WRPGPR_WSBH_FM_MMR6<string instr_asm, bits<10> funct>
+ : MMR6Arch<instr_asm>, MipsR6Inst {
bits<5> rt;
bits<5> rs;
Modified: llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td?rev=333536&r1=333535&r2=333536&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMips32r6InstrInfo.td Wed May 30 05:40:53 2018
@@ -147,8 +147,8 @@ class SW_MMR6_ENC : SW32_FM_MMR6<"sw", 0
class SW16_MMR6_ENC : LOAD_STORE_FM_MM16<0x3a>;
class SWM16_MMR6_ENC : POOL16C_LWM_SWM_FM_MM16R6<0xa>;
class SWSP_MMR6_ENC : LOAD_STORE_SP_FM_MM16<0x32>;
-class WRPGPR_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x3c5>;
-class WSBH_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<0x1ec>;
+class WRPGPR_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<"wrpgpr", 0x3c5>;
+class WSBH_MMR6_ENC : POOL32A_WRPGPR_WSBH_FM_MMR6<"wsbh", 0x1ec>;
class LB_MMR6_ENC : LB32_FM_MMR6;
class LBU_MMR6_ENC : LBU32_FM_MMR6;
class PAUSE_MMR6_ENC : POOL32A_PAUSE_FM_MMR6<"pause", 0b00101>;
@@ -205,11 +205,11 @@ class BOVC_MMR6_ENC : POP35_BOVC_FM_MMR6
class BNVC_MMR6_ENC : POP37_BNVC_FM_MMR6<"bnvc">;
class ADDU16_MMR6_ENC : POOL16A_ADDU16_FM_MMR6;
class AND16_MMR6_ENC : POOL16C_AND16_FM_MMR6;
-class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>, MicroMipsR6Inst16;
+class ANDI16_MMR6_ENC : ANDI_FM_MM16<0b001011>;
class NOT16_MMR6_ENC : POOL16C_NOT16_FM_MMR6;
class OR16_MMR6_ENC : POOL16C_OR16_XOR16_FM_MMR6<0b1001>;
-class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>, MicroMipsR6Inst16;
-class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>, MicroMipsR6Inst16;
+class SLL16_MMR6_ENC : SHIFT_FM_MM16<0>;
+class SRL16_MMR6_ENC : SHIFT_FM_MM16<1>;
class BREAK16_MMR6_ENC : POOL16C_BREAKPOINT_FM_MMR6<0b011011>;
class LI16_MMR6_ENC : LI_FM_MM16;
class MOVE16_MMR6_ENC : MOVE_FM_MM16<0b000011>;
@@ -367,7 +367,7 @@ class BC_MMR6_DESC : BC_MMR6_DESC_BASE<"
class BC16_MMR6_DESC : MicroMipsInst16<(outs), (ins brtarget10_mm:$offset),
!strconcat("bc16", "\t$offset"), [],
II_BC, FrmI>,
- MMR6Arch<"bc16">, MicroMipsR6Inst16 {
+ MMR6Arch<"bc16"> {
let isBranch = 1;
let isTerminator = 1;
let isBarrier = 1;
@@ -377,7 +377,8 @@ class BC16_MMR6_DESC : MicroMipsInst16<(
}
class BEQZC_BNEZC_MM16R6_DESC_BASE<string instr_asm>
- : CBranchZeroMM<instr_asm, brtarget7_mm, GPRMM16Opnd>, MMR6Arch<instr_asm> {
+ : CBranchZeroMM<instr_asm, brtarget7_mm, GPRMM16Opnd>,
+ MMR6Arch<instr_asm> {
let isBranch = 1;
let isTerminator = 1;
let hasDelaySlot = 0;
@@ -454,7 +455,7 @@ class ERETNC_MMR6_DESC : ER_FT<"eretnc",
class JALRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
: MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
[(MipsJmpLink RO:$rs)], II_JALR, FrmR>,
- MMR6Arch<opstr>, MicroMipsR6Inst16 {
+ MMR6Arch<opstr> {
let isCall = 1;
let hasDelaySlot = 0;
let Defs = [RA];
@@ -488,7 +489,7 @@ class JIC_MMR6_DESC : JMP_MMR6_IDX_COMPA
class JRC16_MMR6_DESC_BASE<string opstr, RegisterOperand RO>
: MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
[], II_JR, FrmR>,
- MMR6Arch<opstr>, MicroMipsR6Inst16 {
+ MMR6Arch<opstr> {
let hasDelaySlot = 0;
let isBranch = 1;
let isIndirectBranch = 1;
@@ -498,7 +499,7 @@ class JRC16_MMR6_DESC : JRC16_MMR6_DESC_
class JRCADDIUSP_MMR6_DESC
: MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jrcaddiusp\t$imm",
[], II_JRADDIUSP, FrmR>,
- MMR6Arch<"jrcaddiusp">, MicroMipsR6Inst16 {
+ MMR6Arch<"jrcaddiusp"> {
let hasDelaySlot = 0;
let isTerminator = 1;
let isBarrier = 1;
@@ -636,7 +637,7 @@ class SW_MMR6_DESC : Store<"sw", GPR32Op
InstrItinClass Itinerary = II_SW;
}
class WRPGPR_WSBH_MMR6_DESC_BASE<string instr_asm, RegisterOperand RO,
- InstrItinClass Itin> : MMR6Arch<instr_asm> {
+ InstrItinClass Itin> {
dag InOperandList = (ins RO:$rs);
dag OutOperandList = (outs RO:$rt);
string AsmString = !strconcat(instr_asm, "\t$rt, $rs");
@@ -1096,17 +1097,14 @@ class SLL16_MMR6_DESC : ShiftIMM16<"sll1
MMR6Arch<"sll16">;
class SRL16_MMR6_DESC : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
MMR6Arch<"srl16">;
-class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16", II_BREAK>, MMR6Arch<"break16">,
- MicroMipsR6Inst16;
+class BREAK16_MMR6_DESC : BrkSdbbp16MM<"break16", II_BREAK>, MMR6Arch<"break16">;
class LI16_MMR6_DESC : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>,
- MMR6Arch<"li16">, MicroMipsR6Inst16, IsAsCheapAsAMove;
-class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">,
- MicroMipsR6Inst16;
+ MMR6Arch<"li16">, IsAsCheapAsAMove;
+class MOVE16_MMR6_DESC : MoveMM16<"move16", GPR32Opnd>, MMR6Arch<"move16">;
class MOVEP_MMR6_DESC : MovePMM16<"movep", GPRMM16OpndMoveP>, MMR6Arch<"movep">;
-class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, MMR6Arch<"sdbbp16">,
- MicroMipsR6Inst16;
+class SDBBP16_MMR6_DESC : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, MMR6Arch<"sdbbp16">;
class SUBU16_MMR6_DESC : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
- MMR6Arch<"subu16">, MicroMipsR6Inst16 {
+ MMR6Arch<"subu16"> {
int AddedComplexity = 1;
}
class XOR16_MMR6_DESC : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR>,
@@ -1166,7 +1164,7 @@ class LWM16_MMR6_DESC
: MicroMipsInst16<(outs reglist16:$rt), (ins mem_mm_4sp:$addr),
!strconcat("lwm16", "\t$rt, $addr"), [],
II_LWM, FrmI>,
- MMR6Arch<"lwm16">, MicroMipsR6Inst16 {
+ MMR6Arch<"lwm16"> {
let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
let mayLoad = 1;
ComplexPattern Addr = addr;
@@ -1176,7 +1174,7 @@ class SWM16_MMR6_DESC
: MicroMipsInst16<(outs), (ins reglist16:$rt, mem_mm_4sp:$addr),
!strconcat("swm16", "\t$rt, $addr"), [],
II_SWM, FrmI>,
- MMR6Arch<"swm16">, MicroMipsR6Inst16 {
+ MMR6Arch<"swm16"> {
let DecoderMethod = "DecodeMemMMReglistImm4Lsl2";
let mayStore = 1;
ComplexPattern Addr = addr;
@@ -1187,7 +1185,7 @@ class SB16_MMR6_DESC_BASE<string opstr,
Operand MemOpnd>
: MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr),
!strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI>,
- MMR6Arch<opstr>, MicroMipsR6Inst16 {
+ MMR6Arch<opstr> {
let DecoderMethod = "DecodeMemMMImm4";
let mayStore = 1;
}
@@ -1201,7 +1199,7 @@ class SW16_MMR6_DESC : SB16_MMR6_DESC_BA
class SWSP_MMR6_DESC
: MicroMipsInst16<(outs), (ins GPR32Opnd:$rt, mem_mm_sp_imm5_lsl2:$offset),
!strconcat("sw", "\t$rt, $offset"), [], II_SW, FrmI>,
- MMR6Arch<"sw">, MicroMipsR6Inst16 {
+ MMR6Arch<"sw"> {
let DecoderMethod = "DecodeMemMMSPImm5Lsl2";
let mayStore = 1;
}
@@ -1370,6 +1368,7 @@ def GINVI_MMR6 : R6MMR6Rel, GINVI_MMR6_E
ISA_MICROMIPS32R6, ASE_GINV;
def GINVT_MMR6 : R6MMR6Rel, GINVT_MMR6_ENC, GINVT_MMR6_DESC,
ISA_MICROMIPS32R6, ASE_GINV;
+let FastISelShouldIgnore = 1 in
def JALRC16_MMR6 : R6MMR6Rel, JALRC16_MMR6_DESC, JALRC16_MMR6_ENC,
ISA_MICROMIPS32R6;
def JIALC_MMR6 : R6MMR6Rel, JIALC_MMR6_ENC, JIALC_MMR6_DESC, ISA_MICROMIPS32R6;
Modified: llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrFormats.td?rev=333536&r1=333535&r2=333536&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsDSPInstrFormats.td Wed May 30 05:40:53 2018
@@ -8,7 +8,7 @@
//===----------------------------------------------------------------------===//
class MMDSPInst<string opstr = "">
- : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl {
+ : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
let ASEPredicate = [HasDSP];
let AdditionalPredicates = [InMicroMips];
string BaseOpcode = opstr;
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td?rev=333536&r1=333535&r2=333536&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFormats.td Wed May 30 05:40:53 2018
@@ -7,8 +7,8 @@
// This class does not depend on the instruction size.
//
class MicroMipsInstBase<dag outs, dag ins, string asmstr, list<dag> pattern,
- InstrItinClass itin, Format f> : Instruction
-{
+ InstrItinClass itin, Format f> : Instruction,
+ PredicateControl {
let Namespace = "Mips";
let DecoderNamespace = "MicroMips";
@@ -19,7 +19,7 @@ class MicroMipsInstBase<dag outs, dag in
let Pattern = pattern;
let Itinerary = itin;
- let Predicates = [InMicroMips];
+ let EncodingPredicates = [InMicroMips];
Format Form = f;
}
@@ -961,7 +961,7 @@ class LWM_FM_MM<bits<4> funct> : MMArch
let Inst{11-0} = addr{11-0};
}
-class LWM_FM_MM16<bits<4> funct> : MMArch, PredicateControl {
+class LWM_FM_MM16<bits<4> funct> : MMArch {
bits<2> rt;
bits<4> addr;
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td?rev=333536&r1=333535&r2=333536&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td Wed May 30 05:40:53 2018
@@ -422,7 +422,7 @@ class LoadImmMM16<string opstr, Operand
// 16-bit Jump and Link (Call)
class JumpLinkRegMM16<string opstr, RegisterOperand RO> :
MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"),
- [(MipsJmpLink RO:$rs)], II_JALR, FrmR>, PredicateControl {
+ [(MipsJmpLink RO:$rs)], II_JALR, FrmR> {
let isCall = 1;
let hasDelaySlot = 1;
let Defs = [RA];
@@ -612,28 +612,28 @@ class MtCop0MM<string opstr, RegisterOpe
let FastISelShouldIgnore = 1 in {
def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>,
- ARITH_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6;
+ ARITH_FM_MM16<0>, ISA_MICROMIPS32_NOT_MIPS32R6;
def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>,
- LOGIC_FM_MM16<0x2>, ISA_MICROMIPS_NOT_32R6;
+ LOGIC_FM_MM16<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6;
}
def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>,
- ISA_MICROMIPS_NOT_32R6;
+ ISA_MICROMIPS32_NOT_MIPS32R6;
def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>,
- ISA_MICROMIPS_NOT_32R6;
+ ISA_MICROMIPS32_NOT_MIPS32R6;
let FastISelShouldIgnore = 1 in
def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, LOGIC_FM_MM16<0x3>,
- ISA_MICROMIPS_NOT_32R6;
+ ISA_MICROMIPS32_NOT_MIPS32R6;
def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>,
- SHIFT_FM_MM16<0>, ISA_MICROMIPS_NOT_32R6;
+ SHIFT_FM_MM16<0>, ISA_MICROMIPS32_NOT_MIPS32R6;
def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>,
- SHIFT_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6;
+ SHIFT_FM_MM16<1>, ISA_MICROMIPS32_NOT_MIPS32R6;
let FastISelShouldIgnore = 1 in {
def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>,
- ARITH_FM_MM16<1>, ISA_MICROMIPS_NOT_32R6;
+ ARITH_FM_MM16<1>, ISA_MICROMIPS32_NOT_MIPS32R6;
def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>,
- LOGIC_FM_MM16<0x1>, ISA_MICROMIPS_NOT_32R6;
+ LOGIC_FM_MM16<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6;
}
def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU,
mem_mm_4>, LOAD_STORE_FM_MM16<0x02>;
@@ -659,12 +659,12 @@ def ADDIUR2_MM : AddImmUR2<"addiur2", GP
def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
def MFHI16_MM : MoveFromHILOMM<"mfhi16", GPR32Opnd, AC0>,
- MFHILO_FM_MM16<0x10>;
+ MFHILO_FM_MM16<0x10>, ISA_MICROMIPS32_NOT_MIPS32R6;
def MFLO16_MM : MoveFromHILOMM<"mflo16", GPR32Opnd, AC0>,
- MFHILO_FM_MM16<0x12>;
+ MFHILO_FM_MM16<0x12>, ISA_MICROMIPS32_NOT_MIPS32R6;
def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
def MOVEP_MM : MovePMM16<"movep", GPRMM16OpndMoveP>, MOVEP_FM_MM16,
- ISA_MICROMIPS_NOT_32R6;
+ ISA_MICROMIPS32_NOT_MIPS32R6;
def LI16_MM : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>, LI_FM_MM16,
IsAsCheapAsAMove;
def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>,
@@ -679,9 +679,9 @@ def BNEZ16_MM : CBranchZeroMM<"bnez16",
BEQNEZ_FM_MM16<0x2b>;
def B16_MM : UncondBranchMM16<"b16">, B16_FM;
def BREAK16_MM : BrkSdbbp16MM<"break16", II_BREAK>, BRKSDBBP16_FM_MM<0x28>,
- ISA_MICROMIPS_NOT_32R6;
+ ISA_MICROMIPS32_NOT_MIPS32R6;
def SDBBP16_MM : BrkSdbbp16MM<"sdbbp16", II_SDBBP>, BRKSDBBP16_FM_MM<0x2C>,
- ISA_MICROMIPS_NOT_32R6;
+ ISA_MICROMIPS32_NOT_MIPS32R6;
let DecoderNamespace = "MicroMips" in {
/// Load and Store Instructions - multiple
Modified: llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td?rev=333536&r1=333535&r2=333536&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/Mips32r6InstrFormats.td Wed May 30 05:40:53 2018
@@ -30,8 +30,7 @@ class MipsR6Arch<string opstr> {
string BaseOpcode = opstr;
}
-class MipsR6Inst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>,
- PredicateControl {
+class MipsR6Inst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
let DecoderNamespace = "Mips32r6_64r6";
let EncodingPredicates = [HasStdEnc];
}
Modified: llvm/trunk/lib/Target/Mips/MipsDSPInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsDSPInstrFormats.td?rev=333536&r1=333535&r2=333536&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsDSPInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsDSPInstrFormats.td Wed May 30 05:40:53 2018
@@ -45,7 +45,7 @@ def SPECIAL3_OPCODE : Field6<0b011111>;
def REGIMM_OPCODE : Field6<0b000001>;
class DSPInst<string opstr = "">
- : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>, PredicateControl {
+ : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
let ASEPredicate = [HasDSP];
string BaseOpcode = opstr;
string Arch = "dsp";
Modified: llvm/trunk/lib/Target/Mips/MipsEVAInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsEVAInstrFormats.td?rev=333536&r1=333535&r2=333536&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsEVAInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsEVAInstrFormats.td Wed May 30 05:40:53 2018
@@ -12,7 +12,7 @@
//===----------------------------------------------------------------------===//
class MipsEVAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>,
- PredicateControl, StdArch {
+ StdArch {
let DecoderNamespace = "Mips";
let EncodingPredicates = [HasStdEnc];
}
Modified: llvm/trunk/lib/Target/Mips/MipsInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFormats.td?rev=333536&r1=333535&r2=333536&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFormats.td Wed May 30 05:40:53 2018
@@ -70,7 +70,7 @@ class StdArch {
// Generic Mips Format
class MipsInst<dag outs, dag ins, string asmstr, list<dag> pattern,
- InstrItinClass itin, Format f>: Instruction
+ InstrItinClass itin, Format f>: Instruction, PredicateControl
{
field bits<32> Inst;
Format Form = f;
@@ -119,7 +119,7 @@ class MipsInst<dag outs, dag ins, string
// Mips32/64 Instruction Format
class InstSE<dag outs, dag ins, string asmstr, list<dag> pattern,
InstrItinClass itin, Format f, string opstr = ""> :
- MipsInst<outs, ins, asmstr, pattern, itin, f>, PredicateControl {
+ MipsInst<outs, ins, asmstr, pattern, itin, f> {
let EncodingPredicates = [HasStdEnc];
string BaseOpcode = opstr;
string Arch;
@@ -128,7 +128,7 @@ class InstSE<dag outs, dag ins, string a
// Mips Pseudo Instructions Format
class MipsPseudo<dag outs, dag ins, list<dag> pattern,
InstrItinClass itin = IIPseudo> :
- MipsInst<outs, ins, "", pattern, itin, Pseudo>, PredicateControl {
+ MipsInst<outs, ins, "", pattern, itin, Pseudo> {
let isCodeGenOnly = 1;
let isPseudo = 1;
}
@@ -144,7 +144,7 @@ class PseudoSE<dag outs, dag ins, list<d
// These are aliases that require C++ handling to convert to the target
// instruction, while InstAliases can be handled directly by tblgen.
class MipsAsmPseudoInst<dag outs, dag ins, string asmstr>:
- MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo>, PredicateControl {
+ MipsInst<outs, ins, asmstr, [], IIPseudo, Pseudo> {
let isPseudo = 1;
let Pattern = [];
}
Modified: llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td?rev=333536&r1=333535&r2=333536&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsMSAInstrFormats.td Wed May 30 05:40:53 2018
@@ -8,7 +8,7 @@
//===----------------------------------------------------------------------===//
class MSAInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>,
- PredicateControl, ASE_MSA {
+ ASE_MSA {
let EncodingPredicates = [HasStdEnc];
let Inst{31-26} = 0b011110;
}
Modified: llvm/trunk/lib/Target/Mips/MipsMTInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsMTInstrFormats.td?rev=333536&r1=333535&r2=333536&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsMTInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsMTInstrFormats.td Wed May 30 05:40:53 2018
@@ -15,8 +15,7 @@
//
//===----------------------------------------------------------------------===//
-class MipsMTInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther>,
- PredicateControl {
+class MipsMTInst : MipsInst<(outs), (ins), "", [], NoItinerary, FrmOther> {
let DecoderNamespace = "Mips";
let EncodingPredicates = [HasStdEnc];
}
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