[PATCH] D47392: AMDGPU: Always set COMPUTE_PGM_RSRC2.ENABLE_TRAP_HANDLER to zero for AMDHSA as it is set by CP

[Konstantin Zhuravlyov via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL333451: AMDGPU: Always set COMPUTE_PGM_RSRC2.ENABLE_TRAP_HANDLER to zero for AMDHSA as (authored by kzhuravl, committed by ).

Changed prior to commit:
  https://reviews.llvm.org/D47392?vs=148666&id=148960#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D47392

Files:
  llvm/trunk/docs/AMDGPUUsage.rst
  llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
  llvm/trunk/test/CodeGen/AMDGPU/trap.ll


Index: llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
===================================================================
--- llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
+++ llvm/trunk/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
@@ -907,7 +907,8 @@
   ProgInfo.ComputePGMRSrc2 =
       S_00B84C_SCRATCH_EN(ProgInfo.ScratchBlocks > 0) |
       S_00B84C_USER_SGPR(MFI->getNumUserSGPRs()) |
-      S_00B84C_TRAP_HANDLER(STM.isTrapHandlerEnabled()) |
+      // For AMDHSA, TRAP_HANDLER must be zero, as it is populated by the CP.
+      S_00B84C_TRAP_HANDLER(STM.isAmdHsaOS() ? 0 : STM.isTrapHandlerEnabled()) |
       S_00B84C_TGID_X_EN(MFI->hasWorkGroupIDX()) |
       S_00B84C_TGID_Y_EN(MFI->hasWorkGroupIDY()) |
       S_00B84C_TGID_Z_EN(MFI->hasWorkGroupIDZ()) |
Index: llvm/trunk/docs/AMDGPUUsage.rst
===================================================================
--- llvm/trunk/docs/AMDGPUUsage.rst
+++ llvm/trunk/docs/AMDGPUUsage.rst
@@ -1858,17 +1858,13 @@
 
                                                      Used by CP to set up
                                                      ``COMPUTE_PGM_RSRC2.USER_SGPR``.
-     6       1 bit   ENABLE_TRAP_HANDLER             Set to 1 if code contains a
-                                                     TRAP instruction which
-                                                     requires a trap handler to
-                                                     be enabled.
-
-                                                     CP sets
-                                                     ``COMPUTE_PGM_RSRC2.TRAP_PRESENT``
-                                                     if the runtime has
-                                                     installed a trap handler
-                                                     regardless of the setting
-                                                     of this field.
+     6       1 bit   ENABLE_TRAP_HANDLER             Must be 0.
+
+                                                     This bit represents
+                                                     ``COMPUTE_PGM_RSRC2.TRAP_PRESENT``,
+                                                     which is set by the CP if
+                                                     the runtime has installed a
+                                                     trap handler.
      7       1 bit   ENABLE_SGPR_WORKGROUP_ID_X      Enable the setup of the
                                                      system SGPR register for
                                                      the work-group id in the X
Index: llvm/trunk/test/CodeGen/AMDGPU/trap.ll
===================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/trap.ll
+++ llvm/trunk/test/CodeGen/AMDGPU/trap.ll
@@ -26,7 +26,7 @@
 ; NOMESA-TRAP-NEXT: .long   144
 
 ; GCN-LABEL: {{^}}hsa_trap:
-; HSA-TRAP: enable_trap_handler = 1
+; HSA-TRAP: enable_trap_handler = 0
 ; HSA-TRAP: s_mov_b64 s[0:1], s[4:5]
 ; HSA-TRAP: s_trap 2
 
@@ -56,7 +56,7 @@
 
 ; GCN-WARNING: warning: <unknown>:0:0: in function hsa_debugtrap void (i32 addrspace(1)*): debugtrap handler not supported
 ; GCN-LABEL: {{^}}hsa_debugtrap:
-; HSA-TRAP: enable_trap_handler = 1
+; HSA-TRAP: enable_trap_handler = 0
 ; HSA-TRAP: s_trap 3
 ; HSA-TRAP: flat_store_dword v[0:1], v3
 


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