[llvm] r333422 - [AArch64][SVE] Asm: Support for predicated LSL/LSR (vectors)
Sander de Smalen via llvm-commits
llvm-commits at lists.llvm.org
Tue May 29 07:40:24 PDT 2018
Author: s.desmalen
Date: Tue May 29 07:40:24 2018
New Revision: 333422
URL: http://llvm.org/viewvc/llvm-project?rev=333422&view=rev
Log:
[AArch64][SVE] Asm: Support for predicated LSL/LSR (vectors)
Reviewers: rengolin, huntergr, fhahn, samparker, SjoerdMeijer, javed.absar
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D47365
Modified:
llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
llvm/trunk/test/MC/AArch64/SVE/lsl-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/lsl.s
llvm/trunk/test/MC/AArch64/SVE/lsr-diagnostics.s
llvm/trunk/test/MC/AArch64/SVE/lsr.s
Modified: llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td?rev=333422&r1=333421&r2=333422&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64SVEInstrInfo.td Tue May 29 07:40:24 2018
@@ -472,6 +472,8 @@ let Predicates = [HasSVE] in {
defm LSR_ZZI : sve_int_bin_cons_shift_b_right<0b01, "lsr">;
defm LSL_ZZI : sve_int_bin_cons_shift_b_left< 0b11, "lsl">;
+ defm LSR_ZPmZ : sve_int_bin_pred_shift_1<0b001, "lsr">;
+ defm LSL_ZPmZ : sve_int_bin_pred_shift_1<0b011, "lsl">;
// InstAliases
def : InstAlias<"mov $Zd, $Zn",
Modified: llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td?rev=333422&r1=333421&r2=333422&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td (original)
+++ llvm/trunk/lib/Target/AArch64/SVEInstrFormats.td Tue May 29 07:40:24 2018
@@ -598,6 +598,39 @@ multiclass sve_int_index_rr<string asm>
def _S : sve_int_index_rr<0b10, asm, ZPR32, GPR32>;
def _D : sve_int_index_rr<0b11, asm, ZPR64, GPR64>;
}
+//
+//===----------------------------------------------------------------------===//
+// SVE Bitwise Shift - Predicated Group
+//===----------------------------------------------------------------------===//
+
+class sve_int_bin_pred_shift_1<bits<2> sz8_64, bits<3> opc, string asm,
+ ZPRRegOp zprty>
+: I<(outs zprty:$Zdn), (ins PPR3bAny:$Pg, zprty:$_Zdn, zprty:$Zm),
+ asm, "\t$Zdn, $Pg/m, $_Zdn, $Zm",
+ "",
+ []>, Sched<[]> {
+ bits<3> Pg;
+ bits<5> Zdn;
+ bits<5> Zm;
+ let Inst{31-24} = 0b00000100;
+ let Inst{23-22} = sz8_64;
+ let Inst{21-19} = 0b010;
+ let Inst{18-16} = opc;
+ let Inst{15-13} = 0b100;
+ let Inst{12-10} = Pg;
+ let Inst{9-5} = Zm;
+ let Inst{4-0} = Zdn;
+
+ let Constraints = "$Zdn = $_Zdn";
+}
+
+multiclass sve_int_bin_pred_shift_1<bits<3> opc, string asm> {
+ def _B : sve_int_bin_pred_shift_1<0b00, opc, asm, ZPR8>;
+ def _H : sve_int_bin_pred_shift_1<0b01, opc, asm, ZPR16>;
+ def _S : sve_int_bin_pred_shift_1<0b10, opc, asm, ZPR32>;
+ def _D : sve_int_bin_pred_shift_1<0b11, opc, asm, ZPR64>;
+}
+
//===----------------------------------------------------------------------===//
// SVE Shift by Immediate - Unpredicated Group
Modified: llvm/trunk/test/MC/AArch64/SVE/lsl-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/lsl-diagnostics.s?rev=333422&r1=333421&r2=333422&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/lsl-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/lsl-diagnostics.s Tue May 29 07:40:24 2018
@@ -39,3 +39,21 @@ lsl z25.d, z16.d, #64
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 63]
// CHECK-NEXT: lsl z25.d, z16.d, #64
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Source and Destination Registers must match
+lsl z0.b, p0/m, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: lsl z0.b, p0/m, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Element sizes must match
+lsl z0.b, p0/m, z0.b, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: lsl z0.b, p0/m, z0.b, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Predicate not in restricted predicate range
+lsl z0.b, p8/m, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: lsl z0.b, p8/m, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/lsl.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/lsl.s?rev=333422&r1=333421&r2=333422&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/lsl.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/lsl.s Tue May 29 07:40:24 2018
@@ -54,3 +54,27 @@ lsl z31.d, z31.d, #63
// CHECK-ENCODING: [0xff,0x9f,0xff,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 9f ff 04 <unknown>
+
+lsl z0.b, p0/m, z0.b, z0.b
+// CHECK-INST: lsl z0.b, p0/m, z0.b, z0.b
+// CHECK-ENCODING: [0x00,0x80,0x13,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 13 04 <unknown>
+
+lsl z0.h, p0/m, z0.h, z0.h
+// CHECK-INST: lsl z0.h, p0/m, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x80,0x53,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 53 04 <unknown>
+
+lsl z0.s, p0/m, z0.s, z0.s
+// CHECK-INST: lsl z0.s, p0/m, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0x80,0x93,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 93 04 <unknown>
+
+lsl z0.d, p0/m, z0.d, z0.d
+// CHECK-INST: lsl z0.d, p0/m, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x80,0xd3,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 d3 04 <unknown>
Modified: llvm/trunk/test/MC/AArch64/SVE/lsr-diagnostics.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/lsr-diagnostics.s?rev=333422&r1=333421&r2=333422&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/lsr-diagnostics.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/lsr-diagnostics.s Tue May 29 07:40:24 2018
@@ -39,3 +39,21 @@ lsr z26.d, z26.d, #65
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [1, 64]
// CHECK-NEXT: lsr z26.d, z26.d, #65
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Source and Destination Registers must match
+lsr z0.b, p0/m, z1.b, z2.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register
+// CHECK-NEXT: lsr z0.b, p0/m, z1.b, z2.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Element sizes must match
+lsr z0.b, p0/m, z0.b, z1.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: lsr z0.b, p0/m, z0.b, z1.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// Predicate not in restricted predicate range
+lsr z0.b, p8/m, z0.b, z1.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: restricted predicate has range [0, 7].
+// CHECK-NEXT: lsr z0.b, p8/m, z0.b, z1.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
Modified: llvm/trunk/test/MC/AArch64/SVE/lsr.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/AArch64/SVE/lsr.s?rev=333422&r1=333421&r2=333422&view=diff
==============================================================================
--- llvm/trunk/test/MC/AArch64/SVE/lsr.s (original)
+++ llvm/trunk/test/MC/AArch64/SVE/lsr.s Tue May 29 07:40:24 2018
@@ -54,3 +54,27 @@ lsr z31.d, z31.d, #1
// CHECK-ENCODING: [0xff,0x97,0xff,0x04]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff 97 ff 04 <unknown>
+
+lsr z0.b, p0/m, z0.b, z0.b
+// CHECK-INST: lsr z0.b, p0/m, z0.b, z0.b
+// CHECK-ENCODING: [0x00,0x80,0x11,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 11 04 <unknown>
+
+lsr z0.h, p0/m, z0.h, z0.h
+// CHECK-INST: lsr z0.h, p0/m, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0x80,0x51,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 51 04 <unknown>
+
+lsr z0.s, p0/m, z0.s, z0.s
+// CHECK-INST: lsr z0.s, p0/m, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0x80,0x91,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 91 04 <unknown>
+
+lsr z0.d, p0/m, z0.d, z0.d
+// CHECK-INST: lsr z0.d, p0/m, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0x80,0xd1,0x04]
+// CHECK-ERROR: instruction requires: sve
+// CHECK-UNKNOWN: 00 80 d1 04 <unknown>
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