[PATCH] D46870: [MachineScheduler] Don't enforce some hazard checks pre-RA.

[Jonas Paulsson via Phabricator via llvm-commits]

jonpa updated this revision to Diff 148880.
jonpa added a comment.
Herald added a reviewer: javed.absar.

Patch updated so that the checks are done post-RA or pre-RA if target does not do post-RA scheduling. Now only two tests fail.

The ARM test seem to have tested that the cycle is bumped based on BeginGroup/EndGroup flags, which does not now happen.
The SystemZ test now contains one more spill, but I am hoping this disappears once the other scheduling patch for SystemZ also is applied.

On SystemZ, those instructions are quite rare, so it is typically possible to rearrange them post-RA in a constructive way while ignoring them pre-RA. Is this not true on ARM (or other targets)?

Does this patch make sense now? If not, could we add a target flag to control this?


https://reviews.llvm.org/D46870

Files:
  include/llvm/CodeGen/MachineScheduler.h
  lib/CodeGen/MachineScheduler.cpp
  test/CodeGen/ARM/single-issue-r52.mir
  test/CodeGen/SystemZ/int-conv-11.ll

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