[PATCH] D44548: [DAGCombiner] Expand combining of FP logical operations to sign-setting FP operations

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added inline comments.


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Comment at: test/CodeGen/PowerPC/float-logic-ops.ll:4
+; RUN:   -verify-machineinstrs -O2 < %s | FileCheck %s
+define float @absf(float %a) {
+; CHECK-LABEL: absf:
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Separate by newline


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Comment at: test/CodeGen/PowerPC/float-logic-ops.ll:35
+  %conv = bitcast <4 x float> %a to <4 x i32>
+  %and = and <4 x i32> %conv, <i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647>
+  %conv1 = bitcast <4 x i32> %and to <4 x float>
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Would be nice to at least one test with one undef element, and with bad non-splat constant.


Repository:
  rL LLVM

https://reviews.llvm.org/D44548