[PATCH] D47434: AMDGPU: Turn D16 for MIMG instructions into a regular operand

[Nicolai Hähnle via Phabricator via llvm-commits]

nhaehnle created this revision.
nhaehnle added reviewers: arsenm, rampitec, kzhuravl, artem.tamazov, dp, rtaylor.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, wdng.

This allows us to reduce the number of different machine instruction
opcodes, which reduces the table sizes and helps flatten the TableGen
multiclass hierarchies.

We can do this because for each hardware MIMG opcode, we have a full set
of IMAGE_xxx_Vn_Vm machine instructions for all required sizes of vdata
and vaddr registers. Instead of having separate https://reviews.llvm.org/D16 machine instructions,
a packed https://reviews.llvm.org/D16 instructions loading e.g. 4 components can simply use the
same V2 opcode variant that non-D16 instructions use.

We still require a TSFlag for https://reviews.llvm.org/D16 buffer instructions, because the
https://reviews.llvm.org/D16-ness of buffer instructions is part of the opcode. Renaming the flag
should help avoid future confusion.

The one non-obvious code change is that for gather4 instructions, the
disassembler can no longer automatically decide whether to use a V2 or
a V4 variant. The existing logic which choose the correct variant for
other MIMG instruction is extended to cover gather4 as well.

As a bonus, some of the assembler error messages are now more helpful
(e.g., complaining about a wrong data size instead of a non-existing
instruction).

While we're at it, delete a whole bunch of dead legacy TableGen code.

Change-Id: I89b02c2841c06f95e662541433e597f5d4553978


Repository:
  rL LLVM

https://reviews.llvm.org/D47434

Files:
  lib/Target/AMDGPU/AMDGPUInstrInfo.cpp
  lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  lib/Target/AMDGPU/BUFInstructions.td
  lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
  lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.cpp
  lib/Target/AMDGPU/InstPrinter/AMDGPUInstPrinter.h
  lib/Target/AMDGPU/MIMGInstructions.td
  lib/Target/AMDGPU/SIDefines.h
  lib/Target/AMDGPU/SIISelLowering.cpp
  lib/Target/AMDGPU/SIInstrFormats.td
  lib/Target/AMDGPU/SIInstrInfo.h
  lib/Target/AMDGPU/SIInstrInfo.td
  lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
  test/CodeGen/AMDGPU/coalescer-subreg-join.mir
  test/MC/AMDGPU/mimg.s

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