[llvm] r333360 - [X86] Don't hardcode scheduler class
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sun May 27 07:54:19 PDT 2018
Author: rksimon
Date: Sun May 27 07:54:18 2018
New Revision: 333360
URL: http://llvm.org/viewvc/llvm-project?rev=333360&view=rev
Log:
[X86] Don't hardcode scheduler class
Also fixes BEXTRI instruction to use WritBEXTR class, which was missed when the class was added.
Modified:
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/test/CodeGen/X86/tbm-schedule.ll
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=333360&r1=333359&r2=333360&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Sun May 27 07:54:18 2018
@@ -2510,58 +2510,61 @@ let Predicates = [HasTBM], Defs = [EFLAG
multiclass tbm_ternary_imm_intr<bits<8> opc, RegisterClass RC, string OpcodeStr,
X86MemOperand x86memop, PatFrag ld_frag,
Intrinsic Int, Operand immtype,
- SDPatternOperator immoperator> {
+ SDPatternOperator immoperator,
+ X86FoldableSchedWrite Sched> {
def ri : Ii32<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, immtype:$cntl),
!strconcat(OpcodeStr,
"\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
[(set RC:$dst, (Int RC:$src1, immoperator:$cntl))]>,
- XOP, XOPA, Sched<[WriteALU]>;
+ XOP, XOPA, Sched<[Sched]>;
def mi : Ii32<opc, MRMSrcMem, (outs RC:$dst),
(ins x86memop:$src1, immtype:$cntl),
!strconcat(OpcodeStr,
"\t{$cntl, $src1, $dst|$dst, $src1, $cntl}"),
[(set RC:$dst, (Int (ld_frag addr:$src1), immoperator:$cntl))]>,
- XOP, XOPA, Sched<[WriteALULd]>;
+ XOP, XOPA, Sched<[Sched.Folded]>;
}
defm BEXTRI32 : tbm_ternary_imm_intr<0x10, GR32, "bextr{l}", i32mem, loadi32,
- int_x86_tbm_bextri_u32, i32imm, imm>;
+ int_x86_tbm_bextri_u32, i32imm, imm,
+ WriteBEXTR>;
let ImmT = Imm32S in
defm BEXTRI64 : tbm_ternary_imm_intr<0x10, GR64, "bextr{q}", i64mem, loadi64,
int_x86_tbm_bextri_u64, i64i32imm,
- i64immSExt32>, VEX_W;
+ i64immSExt32, WriteBEXTR>, VEX_W;
multiclass tbm_binary_rm<bits<8> opc, Format FormReg, Format FormMem,
RegisterClass RC, string OpcodeStr,
- X86MemOperand x86memop> {
+ X86MemOperand x86memop, X86FoldableSchedWrite Sched> {
let hasSideEffects = 0 in {
def rr : I<opc, FormReg, (outs RC:$dst), (ins RC:$src),
!strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), []>,
- XOP_4V, XOP9, Sched<[WriteALU]>;
+ XOP_4V, XOP9, Sched<[Sched]>;
let mayLoad = 1 in
def rm : I<opc, FormMem, (outs RC:$dst), (ins x86memop:$src),
!strconcat(OpcodeStr,"\t{$src, $dst|$dst, $src}"), []>,
- XOP_4V, XOP9, Sched<[WriteALULd]>;
+ XOP_4V, XOP9, Sched<[Sched.Folded]>;
}
}
multiclass tbm_binary_intr<bits<8> opc, string OpcodeStr,
+ X86FoldableSchedWrite Sched,
Format FormReg, Format FormMem> {
defm NAME#32 : tbm_binary_rm<opc, FormReg, FormMem, GR32, OpcodeStr#"{l}",
- i32mem>;
+ i32mem, Sched>;
defm NAME#64 : tbm_binary_rm<opc, FormReg, FormMem, GR64, OpcodeStr#"{q}",
- i64mem>, VEX_W;
+ i64mem, Sched>, VEX_W;
}
-defm BLCFILL : tbm_binary_intr<0x01, "blcfill", MRM1r, MRM1m>;
-defm BLCI : tbm_binary_intr<0x02, "blci", MRM6r, MRM6m>;
-defm BLCIC : tbm_binary_intr<0x01, "blcic", MRM5r, MRM5m>;
-defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", MRM1r, MRM1m>;
-defm BLCS : tbm_binary_intr<0x01, "blcs", MRM3r, MRM3m>;
-defm BLSFILL : tbm_binary_intr<0x01, "blsfill", MRM2r, MRM2m>;
-defm BLSIC : tbm_binary_intr<0x01, "blsic", MRM6r, MRM6m>;
-defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", MRM7r, MRM7m>;
-defm TZMSK : tbm_binary_intr<0x01, "tzmsk", MRM4r, MRM4m>;
+defm BLCFILL : tbm_binary_intr<0x01, "blcfill", WriteALU, MRM1r, MRM1m>;
+defm BLCI : tbm_binary_intr<0x02, "blci", WriteALU, MRM6r, MRM6m>;
+defm BLCIC : tbm_binary_intr<0x01, "blcic", WriteALU, MRM5r, MRM5m>;
+defm BLCMSK : tbm_binary_intr<0x02, "blcmsk", WriteALU, MRM1r, MRM1m>;
+defm BLCS : tbm_binary_intr<0x01, "blcs", WriteALU, MRM3r, MRM3m>;
+defm BLSFILL : tbm_binary_intr<0x01, "blsfill", WriteALU, MRM2r, MRM2m>;
+defm BLSIC : tbm_binary_intr<0x01, "blsic", WriteALU, MRM6r, MRM6m>;
+defm T1MSKC : tbm_binary_intr<0x01, "t1mskc", WriteALU, MRM7r, MRM7m>;
+defm TZMSK : tbm_binary_intr<0x01, "tzmsk", WriteALU, MRM4r, MRM4m>;
} // HasTBM, EFLAGS
// Use BEXTRI for 64-bit 'and' with large immediate 'mask'.
Modified: llvm/trunk/test/CodeGen/X86/tbm-schedule.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/tbm-schedule.ll?rev=333360&r1=333359&r2=333360&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/tbm-schedule.ll (original)
+++ llvm/trunk/test/CodeGen/X86/tbm-schedule.ll Sun May 27 07:54:18 2018
@@ -8,9 +8,9 @@ define i32 @test_x86_tbm_bextri_u32(i32
; GENERIC-LABEL: test_x86_tbm_bextri_u32:
; GENERIC: # %bb.0:
; GENERIC-NEXT: bextrl $3076, %edi, %ecx # imm = 0xC04
-; GENERIC-NEXT: # sched: [1:0.33]
+; GENERIC-NEXT: # sched: [2:1.00]
; GENERIC-NEXT: bextrl $3076, (%rsi), %eax # imm = 0xC04
-; GENERIC-NEXT: # sched: [6:0.50]
+; GENERIC-NEXT: # sched: [7:1.00]
; GENERIC-NEXT: addl %ecx, %eax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
@@ -33,9 +33,9 @@ define i64 @test_x86_tbm_bextri_u64(i64
; GENERIC-LABEL: test_x86_tbm_bextri_u64:
; GENERIC: # %bb.0:
; GENERIC-NEXT: bextrl $3076, %edi, %ecx # imm = 0xC04
-; GENERIC-NEXT: # sched: [1:0.33]
+; GENERIC-NEXT: # sched: [2:1.00]
; GENERIC-NEXT: bextrl $3076, (%rsi), %eax # imm = 0xC04
-; GENERIC-NEXT: # sched: [6:0.50]
+; GENERIC-NEXT: # sched: [7:1.00]
; GENERIC-NEXT: addq %rcx, %rax # sched: [1:0.33]
; GENERIC-NEXT: retq # sched: [1:1.00]
;
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