[PATCH] D47012: [X86] Scalar mask and scalar move optimizations

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: lib/Target/X86/X86ISelLowering.cpp:32207
+      // LHS and RHS swapped due to
+      // setcc outputting 1 when AND resulted in 0 and vice versa.
+      return DAG.getNode(ISD::SELECT, DL, VT, AndNode, RHS, LHS);
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You might still need a truncate on the AND if it isn't an i8


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Comment at: lib/Target/X86/X86InstrFMA.td:369
+                               ValueType VT, ValueType EltVT> {
+  let Predicates = [HasFMA] in {
+    def : Pat<(VT (Move (VT VR128:$src2), (VT (scalar_to_vector
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This should be [HasFMA, NoAVX512]. And the AVX512InstrInfo.td needs an equivalent set of patterns mapped to the unmasked EVEX instructions.


Repository:
  rL LLVM

https://reviews.llvm.org/D47012