[PATCH] D47239: [InstCombine] Combine XOR and AES insructions on ARM/ARM64

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: test/Transforms/InstCombine/AArch64/aes-intrinsics.ll:21
+}
+
+declare <16 x i8> @llvm.aarch64.crypto.aese(<16 x i8>, <16 x i8>) #1
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Would it be useful to add some negative tests in case the second operand is not all zero?


Repository:
  rL LLVM

https://reviews.llvm.org/D47239