[PATCH] D47012: [X86] Scalar mask and scalar move optimizations

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: lib/Target/X86/X86ISelLowering.cpp:32216
+        Mask = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, Mask);
+      return DAG.getNode(ISD::SELECT, DL, VT, Mask, RHS, LHS);
+    }
----------------
I don't know if you can use ISD::SELECT here if you don't have the ANDing with 1. ISD::SELECT definition is that the condition value is either 0 or 1 regardless of how many bits it is. If you pass in the raw X you violate this rule.


Repository:
  rL LLVM

https://reviews.llvm.org/D47012