[llvm] r333009 - [Hexagon] Add patterns for accumulating HVX compares
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Tue May 22 11:27:02 PDT 2018
Author: kparzysz
Date: Tue May 22 11:27:02 2018
New Revision: 333009
URL: http://llvm.org/viewvc/llvm-project?rev=333009&view=rev
Log:
[Hexagon] Add patterns for accumulating HVX compares
Modified:
llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td
llvm/trunk/lib/Target/Hexagon/HexagonPatternsHVX.td
llvm/trunk/test/CodeGen/Hexagon/autohvx/bitwise-pred-128b.ll
llvm/trunk/test/CodeGen/Hexagon/autohvx/bitwise-pred-64b.ll
llvm/trunk/test/CodeGen/Hexagon/autohvx/vector-compare-128b.ll
llvm/trunk/test/CodeGen/Hexagon/autohvx/vector-compare-64b.ll
Modified: llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td?rev=333009&r1=333008&r2=333009&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td Tue May 22 11:27:02 2018
@@ -282,9 +282,9 @@ class AccRRI_pat<InstHexagon MI, PatFrag
(MI RegPred:$Rx, RegPred:$Rs, imm:$I)>;
class AccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op,
- PatFrag RsPred, PatFrag RtPred>
- : Pat<(AccOp RsPred:$Rx, (Op RsPred:$Rs, RtPred:$Rt)),
- (MI RsPred:$Rx, RsPred:$Rs, RtPred:$Rt)>;
+ PatFrag RxPred, PatFrag RsPred, PatFrag RtPred>
+ : Pat<(AccOp RxPred:$Rx, (Op RsPred:$Rs, RtPred:$Rt)),
+ (MI RxPred:$Rx, RsPred:$Rs, RtPred:$Rt)>;
multiclass SelMinMax_pats<PatFrag CmpOp, PatFrag Val,
InstHexagon InstA, InstHexagon InstB> {
@@ -489,10 +489,10 @@ multiclass BoolOpR_RR_pat<InstHexagon MI
}
multiclass BoolAccRRR_pat<InstHexagon MI, PatFrag AccOp, PatFrag Op> {
- def: AccRRR_pat<MI, AccOp, Op, I1, I1>;
- def: AccRRR_pat<MI, AccOp, Op, V2I1, V2I1>;
- def: AccRRR_pat<MI, AccOp, Op, V4I1, V4I1>;
- def: AccRRR_pat<MI, AccOp, Op, V8I1, V8I1>;
+ def: AccRRR_pat<MI, AccOp, Op, I1, I1, I1>;
+ def: AccRRR_pat<MI, AccOp, Op, V2I1, V2I1, V2I1>;
+ def: AccRRR_pat<MI, AccOp, Op, V4I1, V4I1, V4I1>;
+ def: AccRRR_pat<MI, AccOp, Op, V8I1, V8I1, V8I1>;
}
defm: BoolOpR_RR_pat<C2_and, And>;
@@ -1036,38 +1036,38 @@ let AddedComplexity = 100 in {
}
let AddedComplexity = 100 in {
- def: AccRRR_pat<S2_asr_r_r_acc, Add, Su<Sra>, I32, I32>;
- def: AccRRR_pat<S2_asr_r_r_nac, Sub, Su<Sra>, I32, I32>;
- def: AccRRR_pat<S2_asr_r_r_and, And, Su<Sra>, I32, I32>;
- def: AccRRR_pat<S2_asr_r_r_or, Or, Su<Sra>, I32, I32>;
-
- def: AccRRR_pat<S2_asr_r_p_acc, Add, Su<Sra>, I64, I32>;
- def: AccRRR_pat<S2_asr_r_p_nac, Sub, Su<Sra>, I64, I32>;
- def: AccRRR_pat<S2_asr_r_p_and, And, Su<Sra>, I64, I32>;
- def: AccRRR_pat<S2_asr_r_p_or, Or, Su<Sra>, I64, I32>;
- def: AccRRR_pat<S2_asr_r_p_xor, Xor, Su<Sra>, I64, I32>;
-
- def: AccRRR_pat<S2_lsr_r_r_acc, Add, Su<Srl>, I32, I32>;
- def: AccRRR_pat<S2_lsr_r_r_nac, Sub, Su<Srl>, I32, I32>;
- def: AccRRR_pat<S2_lsr_r_r_and, And, Su<Srl>, I32, I32>;
- def: AccRRR_pat<S2_lsr_r_r_or, Or, Su<Srl>, I32, I32>;
-
- def: AccRRR_pat<S2_lsr_r_p_acc, Add, Su<Srl>, I64, I32>;
- def: AccRRR_pat<S2_lsr_r_p_nac, Sub, Su<Srl>, I64, I32>;
- def: AccRRR_pat<S2_lsr_r_p_and, And, Su<Srl>, I64, I32>;
- def: AccRRR_pat<S2_lsr_r_p_or, Or, Su<Srl>, I64, I32>;
- def: AccRRR_pat<S2_lsr_r_p_xor, Xor, Su<Srl>, I64, I32>;
-
- def: AccRRR_pat<S2_asl_r_r_acc, Add, Su<Shl>, I32, I32>;
- def: AccRRR_pat<S2_asl_r_r_nac, Sub, Su<Shl>, I32, I32>;
- def: AccRRR_pat<S2_asl_r_r_and, And, Su<Shl>, I32, I32>;
- def: AccRRR_pat<S2_asl_r_r_or, Or, Su<Shl>, I32, I32>;
-
- def: AccRRR_pat<S2_asl_r_p_acc, Add, Su<Shl>, I64, I32>;
- def: AccRRR_pat<S2_asl_r_p_nac, Sub, Su<Shl>, I64, I32>;
- def: AccRRR_pat<S2_asl_r_p_and, And, Su<Shl>, I64, I32>;
- def: AccRRR_pat<S2_asl_r_p_or, Or, Su<Shl>, I64, I32>;
- def: AccRRR_pat<S2_asl_r_p_xor, Xor, Su<Shl>, I64, I32>;
+ def: AccRRR_pat<S2_asr_r_r_acc, Add, Su<Sra>, I32, I32, I32>;
+ def: AccRRR_pat<S2_asr_r_r_nac, Sub, Su<Sra>, I32, I32, I32>;
+ def: AccRRR_pat<S2_asr_r_r_and, And, Su<Sra>, I32, I32, I32>;
+ def: AccRRR_pat<S2_asr_r_r_or, Or, Su<Sra>, I32, I32, I32>;
+
+ def: AccRRR_pat<S2_asr_r_p_acc, Add, Su<Sra>, I64, I64, I32>;
+ def: AccRRR_pat<S2_asr_r_p_nac, Sub, Su<Sra>, I64, I64, I32>;
+ def: AccRRR_pat<S2_asr_r_p_and, And, Su<Sra>, I64, I64, I32>;
+ def: AccRRR_pat<S2_asr_r_p_or, Or, Su<Sra>, I64, I64, I32>;
+ def: AccRRR_pat<S2_asr_r_p_xor, Xor, Su<Sra>, I64, I64, I32>;
+
+ def: AccRRR_pat<S2_lsr_r_r_acc, Add, Su<Srl>, I32, I32, I32>;
+ def: AccRRR_pat<S2_lsr_r_r_nac, Sub, Su<Srl>, I32, I32, I32>;
+ def: AccRRR_pat<S2_lsr_r_r_and, And, Su<Srl>, I32, I32, I32>;
+ def: AccRRR_pat<S2_lsr_r_r_or, Or, Su<Srl>, I32, I32, I32>;
+
+ def: AccRRR_pat<S2_lsr_r_p_acc, Add, Su<Srl>, I64, I64, I32>;
+ def: AccRRR_pat<S2_lsr_r_p_nac, Sub, Su<Srl>, I64, I64, I32>;
+ def: AccRRR_pat<S2_lsr_r_p_and, And, Su<Srl>, I64, I64, I32>;
+ def: AccRRR_pat<S2_lsr_r_p_or, Or, Su<Srl>, I64, I64, I32>;
+ def: AccRRR_pat<S2_lsr_r_p_xor, Xor, Su<Srl>, I64, I64, I32>;
+
+ def: AccRRR_pat<S2_asl_r_r_acc, Add, Su<Shl>, I32, I32, I32>;
+ def: AccRRR_pat<S2_asl_r_r_nac, Sub, Su<Shl>, I32, I32, I32>;
+ def: AccRRR_pat<S2_asl_r_r_and, And, Su<Shl>, I32, I32, I32>;
+ def: AccRRR_pat<S2_asl_r_r_or, Or, Su<Shl>, I32, I32, I32>;
+
+ def: AccRRR_pat<S2_asl_r_p_acc, Add, Su<Shl>, I64, I64, I32>;
+ def: AccRRR_pat<S2_asl_r_p_nac, Sub, Su<Shl>, I64, I64, I32>;
+ def: AccRRR_pat<S2_asl_r_p_and, And, Su<Shl>, I64, I64, I32>;
+ def: AccRRR_pat<S2_asl_r_p_or, Or, Su<Shl>, I64, I64, I32>;
+ def: AccRRR_pat<S2_asl_r_p_xor, Xor, Su<Shl>, I64, I64, I32>;
}
@@ -1257,12 +1257,12 @@ let Predicates = [HasV5T] in {
let AddedComplexity = 10 in {
def: AccRRI_pat<M2_macsip, Add, Su<Mul>, I32, u32_0ImmPred>;
def: AccRRI_pat<M2_macsin, Sub, Su<Mul>, I32, u32_0ImmPred>;
- def: AccRRR_pat<M2_maci, Add, Su<Mul>, I32, I32>;
+ def: AccRRR_pat<M2_maci, Add, Su<Mul>, I32, I32, I32>;
}
def: AccRRI_pat<M2_naccii, Sub, Su<Add>, I32, s32_0ImmPred>;
def: AccRRI_pat<M2_accii, Add, Su<Add>, I32, s32_0ImmPred>;
-def: AccRRR_pat<M2_acci, Add, Su<Add>, I32, I32>;
+def: AccRRR_pat<M2_acci, Add, Su<Add>, I32, I32, I32>;
// Mulh for vectors
//
@@ -1330,24 +1330,24 @@ def: Pat<(mul I32:$Rs, n8_0ImmPred:$n8),
def: Pat<(add Sext64:$Rs, I64:$Rt),
(A2_addsp (LoReg Sext64:$Rs), I64:$Rt)>;
-def: AccRRR_pat<M4_and_and, And, Su<And>, I32, I32>;
-def: AccRRR_pat<M4_and_or, And, Su<Or>, I32, I32>;
-def: AccRRR_pat<M4_and_xor, And, Su<Xor>, I32, I32>;
-def: AccRRR_pat<M4_or_and, Or, Su<And>, I32, I32>;
-def: AccRRR_pat<M4_or_or, Or, Su<Or>, I32, I32>;
-def: AccRRR_pat<M4_or_xor, Or, Su<Xor>, I32, I32>;
-def: AccRRR_pat<M4_xor_and, Xor, Su<And>, I32, I32>;
-def: AccRRR_pat<M4_xor_or, Xor, Su<Or>, I32, I32>;
-def: AccRRR_pat<M2_xor_xacc, Xor, Su<Xor>, I32, I32>;
-def: AccRRR_pat<M4_xor_xacc, Xor, Su<Xor>, I64, I64>;
+def: AccRRR_pat<M4_and_and, And, Su<And>, I32, I32, I32>;
+def: AccRRR_pat<M4_and_or, And, Su<Or>, I32, I32, I32>;
+def: AccRRR_pat<M4_and_xor, And, Su<Xor>, I32, I32, I32>;
+def: AccRRR_pat<M4_or_and, Or, Su<And>, I32, I32, I32>;
+def: AccRRR_pat<M4_or_or, Or, Su<Or>, I32, I32, I32>;
+def: AccRRR_pat<M4_or_xor, Or, Su<Xor>, I32, I32, I32>;
+def: AccRRR_pat<M4_xor_and, Xor, Su<And>, I32, I32, I32>;
+def: AccRRR_pat<M4_xor_or, Xor, Su<Or>, I32, I32, I32>;
+def: AccRRR_pat<M2_xor_xacc, Xor, Su<Xor>, I32, I32, I32>;
+def: AccRRR_pat<M4_xor_xacc, Xor, Su<Xor>, I64, I64, I64>;
// For dags like (or (and (not _), _), (shl _, _)) where the "or" with
// one argument matches the patterns below, and with the other argument
// matches S2_asl_r_r_or, etc, prefer the patterns below.
let AddedComplexity = 110 in { // greater than S2_asl_r_r_and/or/xor.
- def: AccRRR_pat<M4_and_andn, And, Su<Not2<And>>, I32, I32>;
- def: AccRRR_pat<M4_or_andn, Or, Su<Not2<And>>, I32, I32>;
- def: AccRRR_pat<M4_xor_andn, Xor, Su<Not2<And>>, I32, I32>;
+ def: AccRRR_pat<M4_and_andn, And, Su<Not2<And>>, I32, I32, I32>;
+ def: AccRRR_pat<M4_or_andn, Or, Su<Not2<And>>, I32, I32, I32>;
+ def: AccRRR_pat<M4_xor_andn, Xor, Su<Not2<And>>, I32, I32, I32>;
}
// S4_addaddi and S4_subaddi don't have tied operands, so give them
Modified: llvm/trunk/lib/Target/Hexagon/HexagonPatternsHVX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPatternsHVX.td?rev=333009&r1=333008&r2=333009&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPatternsHVX.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPatternsHVX.td Tue May 22 11:27:02 2018
@@ -242,38 +242,36 @@ let Predicates = [UseHVX] in {
def: Pat<(VecPI16 (HexagonVSPLAT I32:$Rs)), (Rep (Vsplatrh $Rs))>;
def: Pat<(VecPI32 (HexagonVSPLAT I32:$Rs)), (Rep (Vsplatrw $Rs))>;
- def: Pat<(VecI8 (HexagonVSPLATW I32:$Rs)), (V6_lvsplatw I32:$Rs)>;
- def: Pat<(VecI16 (HexagonVSPLATW I32:$Rs)), (V6_lvsplatw I32:$Rs)>;
- def: Pat<(VecI32 (HexagonVSPLATW I32:$Rs)), (V6_lvsplatw I32:$Rs)>;
- def: Pat<(VecPI8 (HexagonVSPLATW I32:$Rs)), (Rep (V6_lvsplatw I32:$Rs))>;
- def: Pat<(VecPI16 (HexagonVSPLATW I32:$Rs)), (Rep (V6_lvsplatw I32:$Rs))>;
- def: Pat<(VecPI32 (HexagonVSPLATW I32:$Rs)), (Rep (V6_lvsplatw I32:$Rs))>;
+ def: Pat<(VecI8 (HexagonVSPLATW I32:$Rs)), (Vsplatrw $Rs)>;
+ def: Pat<(VecI16 (HexagonVSPLATW I32:$Rs)), (Vsplatrw $Rs)>;
+ def: Pat<(VecI32 (HexagonVSPLATW I32:$Rs)), (Vsplatrw $Rs)>;
+ def: Pat<(VecPI8 (HexagonVSPLATW I32:$Rs)), (Rep (Vsplatrw $Rs))>;
+ def: Pat<(VecPI16 (HexagonVSPLATW I32:$Rs)), (Rep (Vsplatrw $Rs))>;
+ def: Pat<(VecPI32 (HexagonVSPLATW I32:$Rs)), (Rep (Vsplatrw $Rs))>;
}
let Predicates = [UseHVX] in {
- def: Pat<(add HVI8:$Vs, HVI8:$Vt), (V6_vaddb HvxVR:$Vs, HvxVR:$Vt)>;
- def: Pat<(add HVI16:$Vs, HVI16:$Vt), (V6_vaddh HvxVR:$Vs, HvxVR:$Vt)>;
- def: Pat<(add HVI32:$Vs, HVI32:$Vt), (V6_vaddw HvxVR:$Vs, HvxVR:$Vt)>;
- def: Pat<(add HWI8:$Vs, HWI8:$Vt), (V6_vaddb_dv HvxWR:$Vs, HvxWR:$Vt)>;
- def: Pat<(add HWI16:$Vs, HWI16:$Vt), (V6_vaddh_dv HvxWR:$Vs, HvxWR:$Vt)>;
- def: Pat<(add HWI32:$Vs, HWI32:$Vt), (V6_vaddw_dv HvxWR:$Vs, HvxWR:$Vt)>;
-
- def: Pat<(sub HVI8:$Vs, HVI8:$Vt), (V6_vsubb HvxVR:$Vs, HvxVR:$Vt)>;
- def: Pat<(sub HVI16:$Vs, HVI16:$Vt), (V6_vsubh HvxVR:$Vs, HvxVR:$Vt)>;
- def: Pat<(sub HVI32:$Vs, HVI32:$Vt), (V6_vsubw HvxVR:$Vs, HvxVR:$Vt)>;
- def: Pat<(sub HWI8:$Vs, HWI8:$Vt), (V6_vsubb_dv HvxWR:$Vs, HvxWR:$Vt)>;
- def: Pat<(sub HWI16:$Vs, HWI16:$Vt), (V6_vsubh_dv HvxWR:$Vs, HvxWR:$Vt)>;
- def: Pat<(sub HWI32:$Vs, HWI32:$Vt), (V6_vsubw_dv HvxWR:$Vs, HvxWR:$Vt)>;
-
- def: Pat<(and HVI8:$Vs, HVI8:$Vt), (V6_vand HvxVR:$Vs, HvxVR:$Vt)>;
- def: Pat<(and HVI16:$Vs, HVI16:$Vt), (V6_vand HvxVR:$Vs, HvxVR:$Vt)>;
- def: Pat<(and HVI32:$Vs, HVI32:$Vt), (V6_vand HvxVR:$Vs, HvxVR:$Vt)>;
- def: Pat<(or HVI8:$Vs, HVI8:$Vt), (V6_vor HvxVR:$Vs, HvxVR:$Vt)>;
- def: Pat<(or HVI16:$Vs, HVI16:$Vt), (V6_vor HvxVR:$Vs, HvxVR:$Vt)>;
- def: Pat<(or HVI32:$Vs, HVI32:$Vt), (V6_vor HvxVR:$Vs, HvxVR:$Vt)>;
- def: Pat<(xor HVI8:$Vs, HVI8:$Vt), (V6_vxor HvxVR:$Vs, HvxVR:$Vt)>;
- def: Pat<(xor HVI16:$Vs, HVI16:$Vt), (V6_vxor HvxVR:$Vs, HvxVR:$Vt)>;
- def: Pat<(xor HVI32:$Vs, HVI32:$Vt), (V6_vxor HvxVR:$Vs, HvxVR:$Vt)>;
+ def: OpR_RR_pat<V6_vaddb, Add, VecI8, HVI8>;
+ def: OpR_RR_pat<V6_vaddh, Add, VecI16, HVI16>;
+ def: OpR_RR_pat<V6_vaddw, Add, VecI32, HVI32>;
+ def: OpR_RR_pat<V6_vaddb_dv, Add, VecPI8, HWI8>;
+ def: OpR_RR_pat<V6_vaddh_dv, Add, VecPI16, HWI16>;
+ def: OpR_RR_pat<V6_vaddw_dv, Add, VecPI32, HWI32>;
+ def: OpR_RR_pat<V6_vsubb, Sub, VecI8, HVI8>;
+ def: OpR_RR_pat<V6_vsubh, Sub, VecI16, HVI16>;
+ def: OpR_RR_pat<V6_vsubw, Sub, VecI32, HVI32>;
+ def: OpR_RR_pat<V6_vsubb_dv, Sub, VecPI8, HWI8>;
+ def: OpR_RR_pat<V6_vsubh_dv, Sub, VecPI16, HWI16>;
+ def: OpR_RR_pat<V6_vsubw_dv, Sub, VecPI32, HWI32>;
+ def: OpR_RR_pat<V6_vand, And, VecI8, HVI8>;
+ def: OpR_RR_pat<V6_vand, And, VecI16, HVI16>;
+ def: OpR_RR_pat<V6_vand, And, VecI32, HVI32>;
+ def: OpR_RR_pat<V6_vor, Or, VecI8, HVI8>;
+ def: OpR_RR_pat<V6_vor, Or, VecI16, HVI16>;
+ def: OpR_RR_pat<V6_vor, Or, VecI32, HVI32>;
+ def: OpR_RR_pat<V6_vxor, Xor, VecI8, HVI8>;
+ def: OpR_RR_pat<V6_vxor, Xor, VecI16, HVI16>;
+ def: OpR_RR_pat<V6_vxor, Xor, VecI32, HVI32>;
def: Pat<(vselect HQ8:$Qu, HVI8:$Vs, HVI8:$Vt),
(V6_vmux HvxQR:$Qu, HvxVR:$Vs, HvxVR:$Vt)>;
@@ -288,7 +286,9 @@ let Predicates = [UseHVX] in {
(V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;
def: Pat<(vselect (qnot HQ32:$Qu), HVI32:$Vs, HVI32:$Vt),
(V6_vmux HvxQR:$Qu, HvxVR:$Vt, HvxVR:$Vs)>;
+}
+let Predicates = [UseHVX] in {
def: Pat<(VecPI16 (sext HVI8:$Vs)), (VSxtb $Vs)>;
def: Pat<(VecPI32 (sext HVI16:$Vs)), (VSxth $Vs)>;
def: Pat<(VecPI16 (zext HVI8:$Vs)), (VZxtb $Vs)>;
@@ -312,6 +312,20 @@ let Predicates = [UseHVX] in {
def: Pat<(VecPI32 (zext_invec HWI8:$Vss)),
(VZxth (LoVec (VZxtb (LoVec $Vss))))>;
+ def: Pat<(VecI8 (trunc HWI16:$Vss)),
+ (V6_vpackeb (HiVec $Vss), (LoVec $Vss))>;
+ def: Pat<(VecI16 (trunc HWI32:$Vss)),
+ (V6_vpackeh (HiVec $Vss), (LoVec $Vss))>;
+
+ def: Pat<(VecQ8 (trunc HVI8:$Vs)),
+ (V6_vandvrt HvxVR:$Vs, (A2_tfrsi 0x01010101))>;
+ def: Pat<(VecQ16 (trunc HVI16:$Vs)),
+ (V6_vandvrt HvxVR:$Vs, (A2_tfrsi 0x01010101))>;
+ def: Pat<(VecQ32 (trunc HVI32:$Vs)),
+ (V6_vandvrt HvxVR:$Vs, (A2_tfrsi 0x01010101))>;
+}
+
+let Predicates = [UseHVX] in {
// The "source" types are not legal, and there are no parameterized
// definitions for them, but they are length-specific.
let Predicates = [UseHVX,UseHVX64B] in {
@@ -360,11 +374,6 @@ let Predicates = [UseHVX] in {
def: Pat<(srl HVI16:$Vs, HVI16:$Vt), (V6_vlsrhv HvxVR:$Vs, HvxVR:$Vt)>;
def: Pat<(srl HVI32:$Vs, HVI32:$Vt), (V6_vlsrwv HvxVR:$Vs, HvxVR:$Vt)>;
- def: Pat<(VecI8 (trunc HWI16:$Vss)),
- (V6_vpackeb (HiVec $Vss), (LoVec $Vss))>;
- def: Pat<(VecI16 (trunc HWI32:$Vss)),
- (V6_vpackeh (HiVec $Vss), (LoVec $Vss))>;
-
def: Pat<(VecI16 (bswap HVI16:$Vs)),
(V6_vdelta HvxVR:$Vs, (V6_lvsplatw (A2_tfrsi 0x01010101)))>;
def: Pat<(VecI32 (bswap HVI32:$Vs)),
@@ -399,43 +408,60 @@ let Predicates = [UseHVX] in {
def: Pat<(qnot HQ16:$Qs), (V6_pred_not HvxQR:$Qs)>;
def: Pat<(qnot HQ32:$Qs), (V6_pred_not HvxQR:$Qs)>;
- def: Pat<(VecQ8 (and HQ8:$Qs, HQ8:$Qt)),
- (V6_pred_and HvxQR:$Qs, HvxQR:$Qt)>;
- def: Pat<(VecQ16 (and HQ16:$Qs, HQ16:$Qt)),
- (V6_pred_and HvxQR:$Qs, HvxQR:$Qt)>;
- def: Pat<(VecQ32 (and HQ32:$Qs, HQ32:$Qt)),
- (V6_pred_and HvxQR:$Qs, HvxQR:$Qt)>;
-
- def: Pat<(VecQ8 (or HQ8:$Qs, HQ8:$Qt)),
- (V6_pred_or HvxQR:$Qs, HvxQR:$Qt)>;
- def: Pat<(VecQ16 (or HQ16:$Qs, HQ16:$Qt)),
- (V6_pred_or HvxQR:$Qs, HvxQR:$Qt)>;
- def: Pat<(VecQ32 (or HQ32:$Qs, HQ32:$Qt)),
- (V6_pred_or HvxQR:$Qs, HvxQR:$Qt)>;
-
- def: Pat<(VecQ8 (xor HQ8:$Qs, HQ8:$Qt)),
- (V6_pred_xor HvxQR:$Qs, HvxQR:$Qt)>;
- def: Pat<(VecQ16 (xor HQ16:$Qs, HQ16:$Qt)),
- (V6_pred_xor HvxQR:$Qs, HvxQR:$Qt)>;
- def: Pat<(VecQ32 (xor HQ32:$Qs, HQ32:$Qt)),
- (V6_pred_xor HvxQR:$Qs, HvxQR:$Qt)>;
-
- def: Pat<(VecQ8 (seteq HVI8:$Vs, HVI8:$Vt)),
- (V6_veqb HvxVR:$Vs, HvxVR:$Vt)>;
- def: Pat<(VecQ8 (setgt HVI8:$Vs, HVI8:$Vt)),
- (V6_vgtb HvxVR:$Vs, HvxVR:$Vt)>;
- def: Pat<(VecQ8 (setugt HVI8:$Vs, HVI8:$Vt)),
- (V6_vgtub HvxVR:$Vs, HvxVR:$Vt)>;
- def: Pat<(VecQ16 (seteq HVI16:$Vs, HVI16:$Vt)),
- (V6_veqh HvxVR:$Vs, HvxVR:$Vt)>;
- def: Pat<(VecQ16 (setgt HVI16:$Vs, HVI16:$Vt)),
- (V6_vgth HvxVR:$Vs, HvxVR:$Vt)>;
- def: Pat<(VecQ16 (setugt HVI16:$Vs, HVI16:$Vt)),
- (V6_vgtuh HvxVR:$Vs, HvxVR:$Vt)>;
- def: Pat<(VecQ32 (seteq HVI32:$Vs, HVI32:$Vt)),
- (V6_veqw HvxVR:$Vs, HvxVR:$Vt)>;
- def: Pat<(VecQ32 (setgt HVI32:$Vs, HVI32:$Vt)),
- (V6_vgtw HvxVR:$Vs, HvxVR:$Vt)>;
- def: Pat<(VecQ32 (setugt HVI32:$Vs, HVI32:$Vt)),
- (V6_vgtuw HvxVR:$Vs, HvxVR:$Vt)>;
+ def: OpR_RR_pat<V6_pred_and, And, VecQ8, HQ8>;
+ def: OpR_RR_pat<V6_pred_and, And, VecQ16, HQ16>;
+ def: OpR_RR_pat<V6_pred_and, And, VecQ32, HQ32>;
+ def: OpR_RR_pat<V6_pred_or, Or, VecQ8, HQ8>;
+ def: OpR_RR_pat<V6_pred_or, Or, VecQ16, HQ16>;
+ def: OpR_RR_pat<V6_pred_or, Or, VecQ32, HQ32>;
+ def: OpR_RR_pat<V6_pred_xor, Xor, VecQ8, HQ8>;
+ def: OpR_RR_pat<V6_pred_xor, Xor, VecQ16, HQ16>;
+ def: OpR_RR_pat<V6_pred_xor, Xor, VecQ32, HQ32>;
+
+ def: OpR_RR_pat<V6_pred_and_n, Not2<And>, VecQ8, HQ8>;
+ def: OpR_RR_pat<V6_pred_and_n, Not2<And>, VecQ16, HQ16>;
+ def: OpR_RR_pat<V6_pred_and_n, Not2<And>, VecQ32, HQ32>;
+ def: OpR_RR_pat<V6_pred_or_n, Not2<Or>, VecQ8, HQ8>;
+ def: OpR_RR_pat<V6_pred_or_n, Not2<Or>, VecQ16, HQ16>;
+ def: OpR_RR_pat<V6_pred_or_n, Not2<Or>, VecQ32, HQ32>;
+
+ def: OpR_RR_pat<V6_veqb, seteq, VecQ8, HVI8>;
+ def: OpR_RR_pat<V6_veqh, seteq, VecQ16, HVI16>;
+ def: OpR_RR_pat<V6_veqw, seteq, VecQ32, HVI32>;
+ def: OpR_RR_pat<V6_vgtb, setgt, VecQ8, HVI8>;
+ def: OpR_RR_pat<V6_vgth, setgt, VecQ16, HVI16>;
+ def: OpR_RR_pat<V6_vgtw, setgt, VecQ32, HVI32>;
+ def: OpR_RR_pat<V6_vgtub, setugt, VecQ8, HVI8>;
+ def: OpR_RR_pat<V6_vgtuh, setugt, VecQ16, HVI16>;
+ def: OpR_RR_pat<V6_vgtuw, setugt, VecQ32, HVI32>;
+
+ def: AccRRR_pat<V6_veqb_and, And, seteq, HQ8, HVI8, HVI8>;
+ def: AccRRR_pat<V6_veqb_or, Or, seteq, HQ8, HVI8, HVI8>;
+ def: AccRRR_pat<V6_veqb_xor, Xor, seteq, HQ8, HVI8, HVI8>;
+ def: AccRRR_pat<V6_veqh_and, And, seteq, HQ16, HVI16, HVI16>;
+ def: AccRRR_pat<V6_veqh_or, Or, seteq, HQ16, HVI16, HVI16>;
+ def: AccRRR_pat<V6_veqh_xor, Xor, seteq, HQ16, HVI16, HVI16>;
+ def: AccRRR_pat<V6_veqw_and, And, seteq, HQ32, HVI32, HVI32>;
+ def: AccRRR_pat<V6_veqw_or, Or, seteq, HQ32, HVI32, HVI32>;
+ def: AccRRR_pat<V6_veqw_xor, Xor, seteq, HQ32, HVI32, HVI32>;
+
+ def: AccRRR_pat<V6_vgtb_and, And, setgt, HQ8, HVI8, HVI8>;
+ def: AccRRR_pat<V6_vgtb_or, Or, setgt, HQ8, HVI8, HVI8>;
+ def: AccRRR_pat<V6_vgtb_xor, Xor, setgt, HQ8, HVI8, HVI8>;
+ def: AccRRR_pat<V6_vgth_and, And, setgt, HQ16, HVI16, HVI16>;
+ def: AccRRR_pat<V6_vgth_or, Or, setgt, HQ16, HVI16, HVI16>;
+ def: AccRRR_pat<V6_vgth_xor, Xor, setgt, HQ16, HVI16, HVI16>;
+ def: AccRRR_pat<V6_vgtw_and, And, setgt, HQ32, HVI32, HVI32>;
+ def: AccRRR_pat<V6_vgtw_or, Or, setgt, HQ32, HVI32, HVI32>;
+ def: AccRRR_pat<V6_vgtw_xor, Xor, setgt, HQ32, HVI32, HVI32>;
+
+ def: AccRRR_pat<V6_vgtub_and, And, setugt, HQ8, HVI8, HVI8>;
+ def: AccRRR_pat<V6_vgtub_or, Or, setugt, HQ8, HVI8, HVI8>;
+ def: AccRRR_pat<V6_vgtub_xor, Xor, setugt, HQ8, HVI8, HVI8>;
+ def: AccRRR_pat<V6_vgtuh_and, And, setugt, HQ16, HVI16, HVI16>;
+ def: AccRRR_pat<V6_vgtuh_or, Or, setugt, HQ16, HVI16, HVI16>;
+ def: AccRRR_pat<V6_vgtuh_xor, Xor, setugt, HQ16, HVI16, HVI16>;
+ def: AccRRR_pat<V6_vgtuw_and, And, setugt, HQ32, HVI32, HVI32>;
+ def: AccRRR_pat<V6_vgtuw_or, Or, setugt, HQ32, HVI32, HVI32>;
+ def: AccRRR_pat<V6_vgtuw_xor, Xor, setugt, HQ32, HVI32, HVI32>;
}
Modified: llvm/trunk/test/CodeGen/Hexagon/autohvx/bitwise-pred-128b.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/autohvx/bitwise-pred-128b.ll?rev=333009&r1=333008&r2=333009&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/autohvx/bitwise-pred-128b.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/autohvx/bitwise-pred-128b.ll Tue May 22 11:27:02 2018
@@ -2,21 +2,21 @@
; CHECK-LABEL: t00
; CHECK: and(q{{[0-3]}},q{{[0-3]}})
-define <128 x i8> @t00(<128 x i8> %a0, <128 x i8> %a1,
- <128 x i8> %a2, <128 x i8> %a3) #0 {
- %q0 = icmp eq <128 x i8> %a0, %a1
- %q1 = icmp eq <128 x i8> %a2, %a3
+define <128 x i8> @t00(<128 x i8> %a0, <128 x i8> %a1) #0 {
+ %q0 = trunc <128 x i8> %a0 to <128 x i1>
+ %q1 = trunc <128 x i8> %a1 to <128 x i1>
%q2 = and <128 x i1> %q0, %q1
%v0 = zext <128 x i1> %q2 to <128 x i8>
ret <128 x i8> %v0
}
+declare <1024 x i1> @llvm.hexagon.vandvrt.128B(<128 x i8>, i32)
+
; CHECK-LABEL: t01
; CHECK: or(q{{[0-3]}},q{{[0-3]}})
-define <128 x i8> @t01(<128 x i8> %a0, <128 x i8> %a1,
- <128 x i8> %a2, <128 x i8> %a3) #0 {
- %q0 = icmp eq <128 x i8> %a0, %a1
- %q1 = icmp eq <128 x i8> %a2, %a3
+define <128 x i8> @t01(<128 x i8> %a0, <128 x i8> %a1) #0 {
+ %q0 = trunc <128 x i8> %a0 to <128 x i1>
+ %q1 = trunc <128 x i8> %a1 to <128 x i1>
%q2 = or <128 x i1> %q0, %q1
%v0 = zext <128 x i1> %q2 to <128 x i8>
ret <128 x i8> %v0
@@ -24,10 +24,9 @@ define <128 x i8> @t01(<128 x i8> %a0, <
; CHECK-LABEL: t02
; CHECK: xor(q{{[0-3]}},q{{[0-3]}})
-define <128 x i8> @t02(<128 x i8> %a0, <128 x i8> %a1,
- <128 x i8> %a2, <128 x i8> %a3) #0 {
- %q0 = icmp eq <128 x i8> %a0, %a1
- %q1 = icmp eq <128 x i8> %a2, %a3
+define <128 x i8> @t02(<128 x i8> %a0, <128 x i8> %a1) #0 {
+ %q0 = trunc <128 x i8> %a0 to <128 x i1>
+ %q1 = trunc <128 x i8> %a1 to <128 x i1>
%q2 = xor <128 x i1> %q0, %q1
%v0 = zext <128 x i1> %q2 to <128 x i8>
ret <128 x i8> %v0
@@ -35,10 +34,9 @@ define <128 x i8> @t02(<128 x i8> %a0, <
; CHECK-LABEL: t10
; CHECK: and(q{{[0-3]}},q{{[0-3]}})
-define <64 x i16> @t10(<64 x i16> %a0, <64 x i16> %a1,
- <64 x i16> %a2, <64 x i16> %a3) #0 {
- %q0 = icmp eq <64 x i16> %a0, %a1
- %q1 = icmp eq <64 x i16> %a2, %a3
+define <64 x i16> @t10(<64 x i16> %a0, <64 x i16> %a1) #0 {
+ %q0 = trunc <64 x i16> %a0 to <64 x i1>
+ %q1 = trunc <64 x i16> %a1 to <64 x i1>
%q2 = and <64 x i1> %q0, %q1
%v0 = zext <64 x i1> %q2 to <64 x i16>
ret <64 x i16> %v0
@@ -46,10 +44,9 @@ define <64 x i16> @t10(<64 x i16> %a0, <
; CHECK-LABEL: t11
; CHECK: or(q{{[0-3]}},q{{[0-3]}})
-define <64 x i16> @t11(<64 x i16> %a0, <64 x i16> %a1,
- <64 x i16> %a2, <64 x i16> %a3) #0 {
- %q0 = icmp eq <64 x i16> %a0, %a1
- %q1 = icmp eq <64 x i16> %a2, %a3
+define <64 x i16> @t11(<64 x i16> %a0, <64 x i16> %a1) #0 {
+ %q0 = trunc <64 x i16> %a0 to <64 x i1>
+ %q1 = trunc <64 x i16> %a1 to <64 x i1>
%q2 = or <64 x i1> %q0, %q1
%v0 = zext <64 x i1> %q2 to <64 x i16>
ret <64 x i16> %v0
@@ -57,10 +54,9 @@ define <64 x i16> @t11(<64 x i16> %a0, <
; CHECK-LABEL: t12
; CHECK: xor(q{{[0-3]}},q{{[0-3]}})
-define <64 x i16> @t12(<64 x i16> %a0, <64 x i16> %a1,
- <64 x i16> %a2, <64 x i16> %a3) #0 {
- %q0 = icmp eq <64 x i16> %a0, %a1
- %q1 = icmp eq <64 x i16> %a2, %a3
+define <64 x i16> @t12(<64 x i16> %a0, <64 x i16> %a1) #0 {
+ %q0 = trunc <64 x i16> %a0 to <64 x i1>
+ %q1 = trunc <64 x i16> %a1 to <64 x i1>
%q2 = xor <64 x i1> %q0, %q1
%v0 = zext <64 x i1> %q2 to <64 x i16>
ret <64 x i16> %v0
@@ -68,10 +64,9 @@ define <64 x i16> @t12(<64 x i16> %a0, <
; CHECK-LABEL: t20
; CHECK: and(q{{[0-3]}},q{{[0-3]}})
-define <32 x i32> @t20(<32 x i32> %a0, <32 x i32> %a1,
- <32 x i32> %a2, <32 x i32> %a3) #0 {
- %q0 = icmp eq <32 x i32> %a0, %a1
- %q1 = icmp eq <32 x i32> %a2, %a3
+define <32 x i32> @t20(<32 x i32> %a0, <32 x i32> %a1) #0 {
+ %q0 = trunc <32 x i32> %a0 to <32 x i1>
+ %q1 = trunc <32 x i32> %a1 to <32 x i1>
%q2 = and <32 x i1> %q0, %q1
%v0 = zext <32 x i1> %q2 to <32 x i32>
ret <32 x i32> %v0
@@ -79,10 +74,9 @@ define <32 x i32> @t20(<32 x i32> %a0, <
; CHECK-LABEL: t21
; CHECK: or(q{{[0-3]}},q{{[0-3]}})
-define <32 x i32> @t21(<32 x i32> %a0, <32 x i32> %a1,
- <32 x i32> %a2, <32 x i32> %a3) #0 {
- %q0 = icmp eq <32 x i32> %a0, %a1
- %q1 = icmp eq <32 x i32> %a2, %a3
+define <32 x i32> @t21(<32 x i32> %a0, <32 x i32> %a1) #0 {
+ %q0 = trunc <32 x i32> %a0 to <32 x i1>
+ %q1 = trunc <32 x i32> %a1 to <32 x i1>
%q2 = or <32 x i1> %q0, %q1
%v0 = zext <32 x i1> %q2 to <32 x i32>
ret <32 x i32> %v0
@@ -90,10 +84,9 @@ define <32 x i32> @t21(<32 x i32> %a0, <
; CHECK-LABEL: t22
; CHECK: xor(q{{[0-3]}},q{{[0-3]}})
-define <32 x i32> @t22(<32 x i32> %a0, <32 x i32> %a1,
- <32 x i32> %a2, <32 x i32> %a3) #0 {
- %q0 = icmp eq <32 x i32> %a0, %a1
- %q1 = icmp eq <32 x i32> %a2, %a3
+define <32 x i32> @t22(<32 x i32> %a0, <32 x i32> %a1) #0 {
+ %q0 = trunc <32 x i32> %a0 to <32 x i1>
+ %q1 = trunc <32 x i32> %a1 to <32 x i1>
%q2 = xor <32 x i1> %q0, %q1
%v0 = zext <32 x i1> %q2 to <32 x i32>
ret <32 x i32> %v0
Modified: llvm/trunk/test/CodeGen/Hexagon/autohvx/bitwise-pred-64b.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/autohvx/bitwise-pred-64b.ll?rev=333009&r1=333008&r2=333009&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/autohvx/bitwise-pred-64b.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/autohvx/bitwise-pred-64b.ll Tue May 22 11:27:02 2018
@@ -2,10 +2,9 @@
; CHECK-LABEL: t00
; CHECK: and(q{{[0-3]}},q{{[0-3]}})
-define <64 x i8> @t00(<64 x i8> %a0, <64 x i8> %a1,
- <64 x i8> %a2, <64 x i8> %a3) #0 {
- %q0 = icmp eq <64 x i8> %a0, %a1
- %q1 = icmp eq <64 x i8> %a2, %a3
+define <64 x i8> @t00(<64 x i8> %a0, <64 x i8> %a1) #0 {
+ %q0 = trunc <64 x i8> %a0 to <64 x i1>
+ %q1 = trunc <64 x i8> %a1 to <64 x i1>
%q2 = and <64 x i1> %q0, %q1
%v0 = zext <64 x i1> %q2 to <64 x i8>
ret <64 x i8> %v0
@@ -13,10 +12,9 @@ define <64 x i8> @t00(<64 x i8> %a0, <64
; CHECK-LABEL: t01
; CHECK: or(q{{[0-3]}},q{{[0-3]}})
-define <64 x i8> @t01(<64 x i8> %a0, <64 x i8> %a1,
- <64 x i8> %a2, <64 x i8> %a3) #0 {
- %q0 = icmp eq <64 x i8> %a0, %a1
- %q1 = icmp eq <64 x i8> %a2, %a3
+define <64 x i8> @t01(<64 x i8> %a0, <64 x i8> %a1) #0 {
+ %q0 = trunc <64 x i8> %a0 to <64 x i1>
+ %q1 = trunc <64 x i8> %a1 to <64 x i1>
%q2 = or <64 x i1> %q0, %q1
%v0 = zext <64 x i1> %q2 to <64 x i8>
ret <64 x i8> %v0
@@ -24,10 +22,9 @@ define <64 x i8> @t01(<64 x i8> %a0, <64
; CHECK-LABEL: t02
; CHECK: xor(q{{[0-3]}},q{{[0-3]}})
-define <64 x i8> @t02(<64 x i8> %a0, <64 x i8> %a1,
- <64 x i8> %a2, <64 x i8> %a3) #0 {
- %q0 = icmp eq <64 x i8> %a0, %a1
- %q1 = icmp eq <64 x i8> %a2, %a3
+define <64 x i8> @t02(<64 x i8> %a0, <64 x i8> %a1) #0 {
+ %q0 = trunc <64 x i8> %a0 to <64 x i1>
+ %q1 = trunc <64 x i8> %a1 to <64 x i1>
%q2 = xor <64 x i1> %q0, %q1
%v0 = zext <64 x i1> %q2 to <64 x i8>
ret <64 x i8> %v0
@@ -35,10 +32,9 @@ define <64 x i8> @t02(<64 x i8> %a0, <64
; CHECK-LABEL: t10
; CHECK: and(q{{[0-3]}},q{{[0-3]}})
-define <32 x i16> @t10(<32 x i16> %a0, <32 x i16> %a1,
- <32 x i16> %a2, <32 x i16> %a3) #0 {
- %q0 = icmp eq <32 x i16> %a0, %a1
- %q1 = icmp eq <32 x i16> %a2, %a3
+define <32 x i16> @t10(<32 x i16> %a0, <32 x i16> %a1) #0 {
+ %q0 = trunc <32 x i16> %a0 to <32 x i1>
+ %q1 = trunc <32 x i16> %a1 to <32 x i1>
%q2 = and <32 x i1> %q0, %q1
%v0 = zext <32 x i1> %q2 to <32 x i16>
ret <32 x i16> %v0
@@ -46,10 +42,9 @@ define <32 x i16> @t10(<32 x i16> %a0, <
; CHECK-LABEL: t11
; CHECK: or(q{{[0-3]}},q{{[0-3]}})
-define <32 x i16> @t11(<32 x i16> %a0, <32 x i16> %a1,
- <32 x i16> %a2, <32 x i16> %a3) #0 {
- %q0 = icmp eq <32 x i16> %a0, %a1
- %q1 = icmp eq <32 x i16> %a2, %a3
+define <32 x i16> @t11(<32 x i16> %a0, <32 x i16> %a1) #0 {
+ %q0 = trunc <32 x i16> %a0 to <32 x i1>
+ %q1 = trunc <32 x i16> %a1 to <32 x i1>
%q2 = or <32 x i1> %q0, %q1
%v0 = zext <32 x i1> %q2 to <32 x i16>
ret <32 x i16> %v0
@@ -57,10 +52,9 @@ define <32 x i16> @t11(<32 x i16> %a0, <
; CHECK-LABEL: t12
; CHECK: xor(q{{[0-3]}},q{{[0-3]}})
-define <32 x i16> @t12(<32 x i16> %a0, <32 x i16> %a1,
- <32 x i16> %a2, <32 x i16> %a3) #0 {
- %q0 = icmp eq <32 x i16> %a0, %a1
- %q1 = icmp eq <32 x i16> %a2, %a3
+define <32 x i16> @t12(<32 x i16> %a0, <32 x i16> %a1) #0 {
+ %q0 = trunc <32 x i16> %a0 to <32 x i1>
+ %q1 = trunc <32 x i16> %a1 to <32 x i1>
%q2 = xor <32 x i1> %q0, %q1
%v0 = zext <32 x i1> %q2 to <32 x i16>
ret <32 x i16> %v0
@@ -68,10 +62,9 @@ define <32 x i16> @t12(<32 x i16> %a0, <
; CHECK-LABEL: t20
; CHECK: and(q{{[0-3]}},q{{[0-3]}})
-define <16 x i32> @t20(<16 x i32> %a0, <16 x i32> %a1,
- <16 x i32> %a2, <16 x i32> %a3) #0 {
- %q0 = icmp eq <16 x i32> %a0, %a1
- %q1 = icmp eq <16 x i32> %a2, %a3
+define <16 x i32> @t20(<16 x i32> %a0, <16 x i32> %a1) #0 {
+ %q0 = trunc <16 x i32> %a0 to <16 x i1>
+ %q1 = trunc <16 x i32> %a1 to <16 x i1>
%q2 = and <16 x i1> %q0, %q1
%v0 = zext <16 x i1> %q2 to <16 x i32>
ret <16 x i32> %v0
@@ -79,10 +72,9 @@ define <16 x i32> @t20(<16 x i32> %a0, <
; CHECK-LABEL: t21
; CHECK: or(q{{[0-3]}},q{{[0-3]}})
-define <16 x i32> @t21(<16 x i32> %a0, <16 x i32> %a1,
- <16 x i32> %a2, <16 x i32> %a3) #0 {
- %q0 = icmp eq <16 x i32> %a0, %a1
- %q1 = icmp eq <16 x i32> %a2, %a3
+define <16 x i32> @t21(<16 x i32> %a0, <16 x i32> %a1) #0 {
+ %q0 = trunc <16 x i32> %a0 to <16 x i1>
+ %q1 = trunc <16 x i32> %a1 to <16 x i1>
%q2 = or <16 x i1> %q0, %q1
%v0 = zext <16 x i1> %q2 to <16 x i32>
ret <16 x i32> %v0
@@ -90,10 +82,9 @@ define <16 x i32> @t21(<16 x i32> %a0, <
; CHECK-LABEL: t22
; CHECK: xor(q{{[0-3]}},q{{[0-3]}})
-define <16 x i32> @t22(<16 x i32> %a0, <16 x i32> %a1,
- <16 x i32> %a2, <16 x i32> %a3) #0 {
- %q0 = icmp eq <16 x i32> %a0, %a1
- %q1 = icmp eq <16 x i32> %a2, %a3
+define <16 x i32> @t22(<16 x i32> %a0, <16 x i32> %a1) #0 {
+ %q0 = trunc <16 x i32> %a0 to <16 x i1>
+ %q1 = trunc <16 x i32> %a1 to <16 x i1>
%q2 = xor <16 x i1> %q0, %q1
%v0 = zext <16 x i1> %q2 to <16 x i32>
ret <16 x i32> %v0
Modified: llvm/trunk/test/CodeGen/Hexagon/autohvx/vector-compare-128b.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/autohvx/vector-compare-128b.ll?rev=333009&r1=333008&r2=333009&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/autohvx/vector-compare-128b.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/autohvx/vector-compare-128b.ll Tue May 22 11:27:02 2018
@@ -92,6 +92,105 @@ define <128 x i8> @test_09(<128 x i8> %v
ret <128 x i8> %t1
}
+; CHECK-LABEL: test_0a:
+; CHECK: q[[Q0A0:[0-3]]] &= vcmp.eq(v0.b,v1.b)
+; CHECK: v0 = vmux(q[[Q0A0]],v0,v1)
+define <128 x i8> @test_0a(<128 x i8> %v0, <128 x i8> %v1, <128 x i8> %v2) #0 {
+ %q0 = icmp eq <128 x i8> %v0, %v1
+ %q1 = trunc <128 x i8> %v2 to <128 x i1>
+ %q2 = and <128 x i1> %q0, %q1
+ %t1 = select <128 x i1> %q2, <128 x i8> %v0, <128 x i8> %v1
+ ret <128 x i8> %t1
+}
+
+; CHECK-LABEL: test_0b:
+; CHECK: q[[Q0B0:[0-3]]] |= vcmp.eq(v0.b,v1.b)
+; CHECK: v0 = vmux(q[[Q0B0]],v0,v1)
+define <128 x i8> @test_0b(<128 x i8> %v0, <128 x i8> %v1, <128 x i8> %v2) #0 {
+ %q0 = icmp eq <128 x i8> %v0, %v1
+ %q1 = trunc <128 x i8> %v2 to <128 x i1>
+ %q2 = or <128 x i1> %q0, %q1
+ %t1 = select <128 x i1> %q2, <128 x i8> %v0, <128 x i8> %v1
+ ret <128 x i8> %t1
+}
+
+; CHECK-LABEL: test_0c:
+; CHECK: q[[Q0C0:[0-3]]] ^= vcmp.eq(v0.b,v1.b)
+; CHECK: v0 = vmux(q[[Q0C0]],v0,v1)
+define <128 x i8> @test_0c(<128 x i8> %v0, <128 x i8> %v1, <128 x i8> %v2) #0 {
+ %q0 = icmp eq <128 x i8> %v0, %v1
+ %q1 = trunc <128 x i8> %v2 to <128 x i1>
+ %q2 = xor <128 x i1> %q0, %q1
+ %t1 = select <128 x i1> %q2, <128 x i8> %v0, <128 x i8> %v1
+ ret <128 x i8> %t1
+}
+
+; CHECK-LABEL: test_0d:
+; CHECK: q[[Q0D0:[0-3]]] &= vcmp.gt(v0.b,v1.b)
+; CHECK: v0 = vmux(q[[Q0D0]],v0,v1)
+define <128 x i8> @test_0d(<128 x i8> %v0, <128 x i8> %v1, <128 x i8> %v2) #0 {
+ %q0 = icmp sgt <128 x i8> %v0, %v1
+ %q1 = trunc <128 x i8> %v2 to <128 x i1>
+ %q2 = and <128 x i1> %q0, %q1
+ %t1 = select <128 x i1> %q2, <128 x i8> %v0, <128 x i8> %v1
+ ret <128 x i8> %t1
+}
+
+; CHECK-LABEL: test_0e:
+; CHECK: q[[Q0E0:[0-3]]] |= vcmp.gt(v0.b,v1.b)
+; CHECK: v0 = vmux(q[[Q0E0]],v0,v1)
+define <128 x i8> @test_0e(<128 x i8> %v0, <128 x i8> %v1, <128 x i8> %v2) #0 {
+ %q0 = icmp sgt <128 x i8> %v0, %v1
+ %q1 = trunc <128 x i8> %v2 to <128 x i1>
+ %q2 = or <128 x i1> %q0, %q1
+ %t1 = select <128 x i1> %q2, <128 x i8> %v0, <128 x i8> %v1
+ ret <128 x i8> %t1
+}
+
+; CHECK-LABEL: test_0f:
+; CHECK: q[[Q0F0:[0-3]]] ^= vcmp.gt(v0.b,v1.b)
+; CHECK: v0 = vmux(q[[Q0F0]],v0,v1)
+define <128 x i8> @test_0f(<128 x i8> %v0, <128 x i8> %v1, <128 x i8> %v2) #0 {
+ %q0 = icmp sgt <128 x i8> %v0, %v1
+ %q1 = trunc <128 x i8> %v2 to <128 x i1>
+ %q2 = xor <128 x i1> %q0, %q1
+ %t1 = select <128 x i1> %q2, <128 x i8> %v0, <128 x i8> %v1
+ ret <128 x i8> %t1
+}
+
+; CHECK-LABEL: test_0g:
+; CHECK: q[[Q0G0:[0-3]]] &= vcmp.gt(v0.ub,v1.ub)
+; CHECK: v0 = vmux(q[[Q0G0]],v0,v1)
+define <128 x i8> @test_0g(<128 x i8> %v0, <128 x i8> %v1, <128 x i8> %v2) #0 {
+ %q0 = icmp ugt <128 x i8> %v0, %v1
+ %q1 = trunc <128 x i8> %v2 to <128 x i1>
+ %q2 = and <128 x i1> %q0, %q1
+ %t1 = select <128 x i1> %q2, <128 x i8> %v0, <128 x i8> %v1
+ ret <128 x i8> %t1
+}
+
+; CHECK-LABEL: test_0h:
+; CHECK: q[[Q0H0:[0-3]]] |= vcmp.gt(v0.ub,v1.ub)
+; CHECK: v0 = vmux(q[[Q0H0]],v0,v1)
+define <128 x i8> @test_0h(<128 x i8> %v0, <128 x i8> %v1, <128 x i8> %v2) #0 {
+ %q0 = icmp ugt <128 x i8> %v0, %v1
+ %q1 = trunc <128 x i8> %v2 to <128 x i1>
+ %q2 = or <128 x i1> %q0, %q1
+ %t1 = select <128 x i1> %q2, <128 x i8> %v0, <128 x i8> %v1
+ ret <128 x i8> %t1
+}
+
+; CHECK-LABEL: test_0i:
+; CHECK: q[[Q0I0:[0-3]]] ^= vcmp.gt(v0.ub,v1.ub)
+; CHECK: v0 = vmux(q[[Q0I0]],v0,v1)
+define <128 x i8> @test_0i(<128 x i8> %v0, <128 x i8> %v1, <128 x i8> %v2) #0 {
+ %q0 = icmp ugt <128 x i8> %v0, %v1
+ %q1 = trunc <128 x i8> %v2 to <128 x i1>
+ %q2 = xor <128 x i1> %q0, %q1
+ %t1 = select <128 x i1> %q2, <128 x i8> %v0, <128 x i8> %v1
+ ret <128 x i8> %t1
+}
+
; --- Half
; CHECK-LABEL: test_10:
@@ -184,6 +283,105 @@ define <64 x i16> @test_19(<64 x i16> %v
ret <64 x i16> %t1
}
+; CHECK-LABEL: test_1a:
+; CHECK: q[[Q1A0:[0-3]]] &= vcmp.eq(v0.h,v1.h)
+; CHECK: v0 = vmux(q[[Q1A0]],v0,v1)
+define <64 x i16> @test_1a(<64 x i16> %v0, <64 x i16> %v1, <64 x i16> %v2) #0 {
+ %q0 = icmp eq <64 x i16> %v0, %v1
+ %q1 = trunc <64 x i16> %v2 to <64 x i1>
+ %q2 = and <64 x i1> %q0, %q1
+ %t1 = select <64 x i1> %q2, <64 x i16> %v0, <64 x i16> %v1
+ ret <64 x i16> %t1
+}
+
+; CHECK-LABEL: test_1b:
+; CHECK: q[[Q1B0:[0-3]]] |= vcmp.eq(v0.h,v1.h)
+; CHECK: v0 = vmux(q[[Q1B0]],v0,v1)
+define <64 x i16> @test_1b(<64 x i16> %v0, <64 x i16> %v1, <64 x i16> %v2) #0 {
+ %q0 = icmp eq <64 x i16> %v0, %v1
+ %q1 = trunc <64 x i16> %v2 to <64 x i1>
+ %q2 = or <64 x i1> %q0, %q1
+ %t1 = select <64 x i1> %q2, <64 x i16> %v0, <64 x i16> %v1
+ ret <64 x i16> %t1
+}
+
+; CHECK-LABEL: test_1c:
+; CHECK: q[[Q1C0:[0-3]]] ^= vcmp.eq(v0.h,v1.h)
+; CHECK: v0 = vmux(q[[Q1C0]],v0,v1)
+define <64 x i16> @test_1c(<64 x i16> %v0, <64 x i16> %v1, <64 x i16> %v2) #0 {
+ %q0 = icmp eq <64 x i16> %v0, %v1
+ %q1 = trunc <64 x i16> %v2 to <64 x i1>
+ %q2 = xor <64 x i1> %q0, %q1
+ %t1 = select <64 x i1> %q2, <64 x i16> %v0, <64 x i16> %v1
+ ret <64 x i16> %t1
+}
+
+; CHECK-LABEL: test_1d:
+; CHECK: q[[Q1D0:[0-3]]] &= vcmp.gt(v0.h,v1.h)
+; CHECK: v0 = vmux(q[[Q1D0]],v0,v1)
+define <64 x i16> @test_1d(<64 x i16> %v0, <64 x i16> %v1, <64 x i16> %v2) #0 {
+ %q0 = icmp sgt <64 x i16> %v0, %v1
+ %q1 = trunc <64 x i16> %v2 to <64 x i1>
+ %q2 = and <64 x i1> %q0, %q1
+ %t1 = select <64 x i1> %q2, <64 x i16> %v0, <64 x i16> %v1
+ ret <64 x i16> %t1
+}
+
+; CHECK-LABEL: test_1e:
+; CHECK: q[[Q1E0:[0-3]]] |= vcmp.gt(v0.h,v1.h)
+; CHECK: v0 = vmux(q[[Q1E0]],v0,v1)
+define <64 x i16> @test_1e(<64 x i16> %v0, <64 x i16> %v1, <64 x i16> %v2) #0 {
+ %q0 = icmp sgt <64 x i16> %v0, %v1
+ %q1 = trunc <64 x i16> %v2 to <64 x i1>
+ %q2 = or <64 x i1> %q0, %q1
+ %t1 = select <64 x i1> %q2, <64 x i16> %v0, <64 x i16> %v1
+ ret <64 x i16> %t1
+}
+
+; CHECK-LABEL: test_1f:
+; CHECK: q[[Q1F0:[0-3]]] ^= vcmp.gt(v0.h,v1.h)
+; CHECK: v0 = vmux(q[[Q1F0]],v0,v1)
+define <64 x i16> @test_1f(<64 x i16> %v0, <64 x i16> %v1, <64 x i16> %v2) #0 {
+ %q0 = icmp sgt <64 x i16> %v0, %v1
+ %q1 = trunc <64 x i16> %v2 to <64 x i1>
+ %q2 = xor <64 x i1> %q0, %q1
+ %t1 = select <64 x i1> %q2, <64 x i16> %v0, <64 x i16> %v1
+ ret <64 x i16> %t1
+}
+
+; CHECK-LABEL: test_1g:
+; CHECK: q[[Q1G0:[0-3]]] &= vcmp.gt(v0.uh,v1.uh)
+; CHECK: v0 = vmux(q[[Q1G0]],v0,v1)
+define <64 x i16> @test_1g(<64 x i16> %v0, <64 x i16> %v1, <64 x i16> %v2) #0 {
+ %q0 = icmp ugt <64 x i16> %v0, %v1
+ %q1 = trunc <64 x i16> %v2 to <64 x i1>
+ %q2 = and <64 x i1> %q0, %q1
+ %t1 = select <64 x i1> %q2, <64 x i16> %v0, <64 x i16> %v1
+ ret <64 x i16> %t1
+}
+
+; CHECK-LABEL: test_1h:
+; CHECK: q[[Q1H0:[0-3]]] |= vcmp.gt(v0.uh,v1.uh)
+; CHECK: v0 = vmux(q[[Q1H0]],v0,v1)
+define <64 x i16> @test_1h(<64 x i16> %v0, <64 x i16> %v1, <64 x i16> %v2) #0 {
+ %q0 = icmp ugt <64 x i16> %v0, %v1
+ %q1 = trunc <64 x i16> %v2 to <64 x i1>
+ %q2 = or <64 x i1> %q0, %q1
+ %t1 = select <64 x i1> %q2, <64 x i16> %v0, <64 x i16> %v1
+ ret <64 x i16> %t1
+}
+
+; CHECK-LABEL: test_1i:
+; CHECK: q[[Q1I0:[0-3]]] ^= vcmp.gt(v0.uh,v1.uh)
+; CHECK: v0 = vmux(q[[Q1I0]],v0,v1)
+define <64 x i16> @test_1i(<64 x i16> %v0, <64 x i16> %v1, <64 x i16> %v2) #0 {
+ %q0 = icmp ugt <64 x i16> %v0, %v1
+ %q1 = trunc <64 x i16> %v2 to <64 x i1>
+ %q2 = xor <64 x i1> %q0, %q1
+ %t1 = select <64 x i1> %q2, <64 x i16> %v0, <64 x i16> %v1
+ ret <64 x i16> %t1
+}
+
; --- Word
; CHECK-LABEL: test_20:
@@ -276,4 +474,103 @@ define <32 x i32> @test_29(<32 x i32> %v
ret <32 x i32> %t1
}
+; CHECK-LABEL: test_2a:
+; CHECK: q[[Q2A0:[0-3]]] &= vcmp.eq(v0.w,v1.w)
+; CHECK: v0 = vmux(q[[Q2A0]],v0,v1)
+define <32 x i32> @test_2a(<32 x i32> %v0, <32 x i32> %v1, <32 x i32> %v2) #0 {
+ %q0 = icmp eq <32 x i32> %v0, %v1
+ %q1 = trunc <32 x i32> %v2 to <32 x i1>
+ %q2 = and <32 x i1> %q0, %q1
+ %t1 = select <32 x i1> %q2, <32 x i32> %v0, <32 x i32> %v1
+ ret <32 x i32> %t1
+}
+
+; CHECK-LABEL: test_2b:
+; CHECK: q[[Q2B0:[0-3]]] |= vcmp.eq(v0.w,v1.w)
+; CHECK: v0 = vmux(q[[Q2B0]],v0,v1)
+define <32 x i32> @test_2b(<32 x i32> %v0, <32 x i32> %v1, <32 x i32> %v2) #0 {
+ %q0 = icmp eq <32 x i32> %v0, %v1
+ %q1 = trunc <32 x i32> %v2 to <32 x i1>
+ %q2 = or <32 x i1> %q0, %q1
+ %t1 = select <32 x i1> %q2, <32 x i32> %v0, <32 x i32> %v1
+ ret <32 x i32> %t1
+}
+
+; CHECK-LABEL: test_2c:
+; CHECK: q[[Q2C0:[0-3]]] ^= vcmp.eq(v0.w,v1.w)
+; CHECK: v0 = vmux(q[[Q2C0]],v0,v1)
+define <32 x i32> @test_2c(<32 x i32> %v0, <32 x i32> %v1, <32 x i32> %v2) #0 {
+ %q0 = icmp eq <32 x i32> %v0, %v1
+ %q1 = trunc <32 x i32> %v2 to <32 x i1>
+ %q2 = xor <32 x i1> %q0, %q1
+ %t1 = select <32 x i1> %q2, <32 x i32> %v0, <32 x i32> %v1
+ ret <32 x i32> %t1
+}
+
+; CHECK-LABEL: test_2d:
+; CHECK: q[[Q2D0:[0-3]]] &= vcmp.gt(v0.w,v1.w)
+; CHECK: v0 = vmux(q[[Q2D0]],v0,v1)
+define <32 x i32> @test_2d(<32 x i32> %v0, <32 x i32> %v1, <32 x i32> %v2) #0 {
+ %q0 = icmp sgt <32 x i32> %v0, %v1
+ %q1 = trunc <32 x i32> %v2 to <32 x i1>
+ %q2 = and <32 x i1> %q0, %q1
+ %t1 = select <32 x i1> %q2, <32 x i32> %v0, <32 x i32> %v1
+ ret <32 x i32> %t1
+}
+
+; CHECK-LABEL: test_2e:
+; CHECK: q[[Q2E0:[0-3]]] |= vcmp.gt(v0.w,v1.w)
+; CHECK: v0 = vmux(q[[Q2E0]],v0,v1)
+define <32 x i32> @test_2e(<32 x i32> %v0, <32 x i32> %v1, <32 x i32> %v2) #0 {
+ %q0 = icmp sgt <32 x i32> %v0, %v1
+ %q1 = trunc <32 x i32> %v2 to <32 x i1>
+ %q2 = or <32 x i1> %q0, %q1
+ %t1 = select <32 x i1> %q2, <32 x i32> %v0, <32 x i32> %v1
+ ret <32 x i32> %t1
+}
+
+; CHECK-LABEL: test_2f:
+; CHECK: q[[Q2F0:[0-3]]] ^= vcmp.gt(v0.w,v1.w)
+; CHECK: v0 = vmux(q[[Q2F0]],v0,v1)
+define <32 x i32> @test_2f(<32 x i32> %v0, <32 x i32> %v1, <32 x i32> %v2) #0 {
+ %q0 = icmp sgt <32 x i32> %v0, %v1
+ %q1 = trunc <32 x i32> %v2 to <32 x i1>
+ %q2 = xor <32 x i1> %q0, %q1
+ %t1 = select <32 x i1> %q2, <32 x i32> %v0, <32 x i32> %v1
+ ret <32 x i32> %t1
+}
+
+; CHECK-LABEL: test_2g:
+; CHECK: q[[Q2G0:[0-3]]] &= vcmp.gt(v0.uw,v1.uw)
+; CHECK: v0 = vmux(q[[Q2G0]],v0,v1)
+define <32 x i32> @test_2g(<32 x i32> %v0, <32 x i32> %v1, <32 x i32> %v2) #0 {
+ %q0 = icmp ugt <32 x i32> %v0, %v1
+ %q1 = trunc <32 x i32> %v2 to <32 x i1>
+ %q2 = and <32 x i1> %q0, %q1
+ %t1 = select <32 x i1> %q2, <32 x i32> %v0, <32 x i32> %v1
+ ret <32 x i32> %t1
+}
+
+; CHECK-LABEL: test_2h:
+; CHECK: q[[Q2H0:[0-3]]] |= vcmp.gt(v0.uw,v1.uw)
+; CHECK: v0 = vmux(q[[Q2H0]],v0,v1)
+define <32 x i32> @test_2h(<32 x i32> %v0, <32 x i32> %v1, <32 x i32> %v2) #0 {
+ %q0 = icmp ugt <32 x i32> %v0, %v1
+ %q1 = trunc <32 x i32> %v2 to <32 x i1>
+ %q2 = or <32 x i1> %q0, %q1
+ %t1 = select <32 x i1> %q2, <32 x i32> %v0, <32 x i32> %v1
+ ret <32 x i32> %t1
+}
+
+; CHECK-LABEL: test_2i:
+; CHECK: q[[Q2I0:[0-3]]] ^= vcmp.gt(v0.uw,v1.uw)
+; CHECK: v0 = vmux(q[[Q2I0]],v0,v1)
+define <32 x i32> @test_2i(<32 x i32> %v0, <32 x i32> %v1, <32 x i32> %v2) #0 {
+ %q0 = icmp ugt <32 x i32> %v0, %v1
+ %q1 = trunc <32 x i32> %v2 to <32 x i1>
+ %q2 = xor <32 x i1> %q0, %q1
+ %t1 = select <32 x i1> %q2, <32 x i32> %v0, <32 x i32> %v1
+ ret <32 x i32> %t1
+}
+
attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length128b" }
Modified: llvm/trunk/test/CodeGen/Hexagon/autohvx/vector-compare-64b.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/autohvx/vector-compare-64b.ll?rev=333009&r1=333008&r2=333009&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/autohvx/vector-compare-64b.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/autohvx/vector-compare-64b.ll Tue May 22 11:27:02 2018
@@ -92,6 +92,106 @@ define <64 x i8> @test_09(<64 x i8> %v0,
ret <64 x i8> %t1
}
+; CHECK-LABEL: test_0a:
+; CHECK: q[[Q0A0:[0-3]]] &= vcmp.eq(v0.b,v1.b)
+; CHECK: v0 = vmux(q[[Q0A0]],v0,v1)
+define <64 x i8> @test_0a(<64 x i8> %v0, <64 x i8> %v1, <64 x i8> %v2) #0 {
+ %q0 = icmp eq <64 x i8> %v0, %v1
+ %q1 = trunc <64 x i8> %v2 to <64 x i1>
+ %q2 = and <64 x i1> %q0, %q1
+ %t1 = select <64 x i1> %q2, <64 x i8> %v0, <64 x i8> %v1
+ ret <64 x i8> %t1
+}
+
+; CHECK-LABEL: test_0b:
+; CHECK: q[[Q0B0:[0-3]]] |= vcmp.eq(v0.b,v1.b)
+; CHECK: v0 = vmux(q[[Q0B0]],v0,v1)
+define <64 x i8> @test_0b(<64 x i8> %v0, <64 x i8> %v1, <64 x i8> %v2) #0 {
+ %q0 = icmp eq <64 x i8> %v0, %v1
+ %q1 = trunc <64 x i8> %v2 to <64 x i1>
+ %q2 = or <64 x i1> %q0, %q1
+ %t1 = select <64 x i1> %q2, <64 x i8> %v0, <64 x i8> %v1
+ ret <64 x i8> %t1
+}
+
+; CHECK-LABEL: test_0c:
+; CHECK: q[[Q0C0:[0-3]]] ^= vcmp.eq(v0.b,v1.b)
+; CHECK: v0 = vmux(q[[Q0C0]],v0,v1)
+define <64 x i8> @test_0c(<64 x i8> %v0, <64 x i8> %v1, <64 x i8> %v2) #0 {
+ %q0 = icmp eq <64 x i8> %v0, %v1
+ %q1 = trunc <64 x i8> %v2 to <64 x i1>
+ %q2 = xor <64 x i1> %q0, %q1
+ %t1 = select <64 x i1> %q2, <64 x i8> %v0, <64 x i8> %v1
+ ret <64 x i8> %t1
+}
+
+; CHECK-LABEL: test_0d:
+; CHECK: q[[Q0D0:[0-3]]] &= vcmp.gt(v0.b,v1.b)
+; CHECK: v0 = vmux(q[[Q0D0]],v0,v1)
+define <64 x i8> @test_0d(<64 x i8> %v0, <64 x i8> %v1, <64 x i8> %v2) #0 {
+ %q0 = icmp sgt <64 x i8> %v0, %v1
+ %q1 = trunc <64 x i8> %v2 to <64 x i1>
+ %q2 = and <64 x i1> %q0, %q1
+ %t1 = select <64 x i1> %q2, <64 x i8> %v0, <64 x i8> %v1
+ ret <64 x i8> %t1
+}
+
+; CHECK-LABEL: test_0e:
+; CHECK: q[[Q0E0:[0-3]]] |= vcmp.gt(v0.b,v1.b)
+; CHECK: v0 = vmux(q[[Q0E0]],v0,v1)
+define <64 x i8> @test_0e(<64 x i8> %v0, <64 x i8> %v1, <64 x i8> %v2) #0 {
+ %q0 = icmp sgt <64 x i8> %v0, %v1
+ %q1 = trunc <64 x i8> %v2 to <64 x i1>
+ %q2 = or <64 x i1> %q0, %q1
+ %t1 = select <64 x i1> %q2, <64 x i8> %v0, <64 x i8> %v1
+ ret <64 x i8> %t1
+}
+
+; CHECK-LABEL: test_0f:
+; CHECK: q[[Q0F0:[0-3]]] ^= vcmp.gt(v0.b,v1.b)
+; CHECK: v0 = vmux(q[[Q0F0]],v0,v1)
+define <64 x i8> @test_0f(<64 x i8> %v0, <64 x i8> %v1, <64 x i8> %v2) #0 {
+ %q0 = icmp sgt <64 x i8> %v0, %v1
+ %q1 = trunc <64 x i8> %v2 to <64 x i1>
+ %q2 = xor <64 x i1> %q0, %q1
+ %t1 = select <64 x i1> %q2, <64 x i8> %v0, <64 x i8> %v1
+ ret <64 x i8> %t1
+}
+
+; CHECK-LABEL: test_0g:
+; CHECK: q[[Q0G0:[0-3]]] &= vcmp.gt(v0.ub,v1.ub)
+; CHECK: v0 = vmux(q[[Q0G0]],v0,v1)
+define <64 x i8> @test_0g(<64 x i8> %v0, <64 x i8> %v1, <64 x i8> %v2) #0 {
+ %q0 = icmp ugt <64 x i8> %v0, %v1
+ %q1 = trunc <64 x i8> %v2 to <64 x i1>
+ %q2 = and <64 x i1> %q0, %q1
+ %t1 = select <64 x i1> %q2, <64 x i8> %v0, <64 x i8> %v1
+ ret <64 x i8> %t1
+}
+
+; CHECK-LABEL: test_0h:
+; CHECK: q[[Q0H0:[0-3]]] |= vcmp.gt(v0.ub,v1.ub)
+; CHECK: v0 = vmux(q[[Q0H0]],v0,v1)
+define <64 x i8> @test_0h(<64 x i8> %v0, <64 x i8> %v1, <64 x i8> %v2) #0 {
+ %q0 = icmp ugt <64 x i8> %v0, %v1
+ %q1 = trunc <64 x i8> %v2 to <64 x i1>
+ %q2 = or <64 x i1> %q0, %q1
+ %t1 = select <64 x i1> %q2, <64 x i8> %v0, <64 x i8> %v1
+ ret <64 x i8> %t1
+}
+
+; CHECK-LABEL: test_0i:
+; CHECK: q[[Q0I0:[0-3]]] ^= vcmp.gt(v0.ub,v1.ub)
+; CHECK: v0 = vmux(q[[Q0I0]],v0,v1)
+define <64 x i8> @test_0i(<64 x i8> %v0, <64 x i8> %v1, <64 x i8> %v2) #0 {
+ %q0 = icmp ugt <64 x i8> %v0, %v1
+ %q1 = trunc <64 x i8> %v2 to <64 x i1>
+ %q2 = xor <64 x i1> %q0, %q1
+ %t1 = select <64 x i1> %q2, <64 x i8> %v0, <64 x i8> %v1
+ ret <64 x i8> %t1
+}
+
+
; --- Half
; CHECK-LABEL: test_10:
@@ -184,6 +284,105 @@ define <32 x i16> @test_19(<32 x i16> %v
ret <32 x i16> %t1
}
+; CHECK-LABEL: test_1a:
+; CHECK: q[[Q1A0:[0-3]]] &= vcmp.eq(v0.h,v1.h)
+; CHECK: v0 = vmux(q[[Q1A0]],v0,v1)
+define <32 x i16> @test_1a(<32 x i16> %v0, <32 x i16> %v1, <32 x i16> %v2) #0 {
+ %q0 = icmp eq <32 x i16> %v0, %v1
+ %q1 = trunc <32 x i16> %v2 to <32 x i1>
+ %q2 = and <32 x i1> %q0, %q1
+ %t1 = select <32 x i1> %q2, <32 x i16> %v0, <32 x i16> %v1
+ ret <32 x i16> %t1
+}
+
+; CHECK-LABEL: test_1b:
+; CHECK: q[[Q1B0:[0-3]]] |= vcmp.eq(v0.h,v1.h)
+; CHECK: v0 = vmux(q[[Q1B0]],v0,v1)
+define <32 x i16> @test_1b(<32 x i16> %v0, <32 x i16> %v1, <32 x i16> %v2) #0 {
+ %q0 = icmp eq <32 x i16> %v0, %v1
+ %q1 = trunc <32 x i16> %v2 to <32 x i1>
+ %q2 = or <32 x i1> %q0, %q1
+ %t1 = select <32 x i1> %q2, <32 x i16> %v0, <32 x i16> %v1
+ ret <32 x i16> %t1
+}
+
+; CHECK-LABEL: test_1c:
+; CHECK: q[[Q1C0:[0-3]]] ^= vcmp.eq(v0.h,v1.h)
+; CHECK: v0 = vmux(q[[Q1C0]],v0,v1)
+define <32 x i16> @test_1c(<32 x i16> %v0, <32 x i16> %v1, <32 x i16> %v2) #0 {
+ %q0 = icmp eq <32 x i16> %v0, %v1
+ %q1 = trunc <32 x i16> %v2 to <32 x i1>
+ %q2 = xor <32 x i1> %q0, %q1
+ %t1 = select <32 x i1> %q2, <32 x i16> %v0, <32 x i16> %v1
+ ret <32 x i16> %t1
+}
+
+; CHECK-LABEL: test_1d:
+; CHECK: q[[Q1D0:[0-3]]] &= vcmp.gt(v0.h,v1.h)
+; CHECK: v0 = vmux(q[[Q1D0]],v0,v1)
+define <32 x i16> @test_1d(<32 x i16> %v0, <32 x i16> %v1, <32 x i16> %v2) #0 {
+ %q0 = icmp sgt <32 x i16> %v0, %v1
+ %q1 = trunc <32 x i16> %v2 to <32 x i1>
+ %q2 = and <32 x i1> %q0, %q1
+ %t1 = select <32 x i1> %q2, <32 x i16> %v0, <32 x i16> %v1
+ ret <32 x i16> %t1
+}
+
+; CHECK-LABEL: test_1e:
+; CHECK: q[[Q1E0:[0-3]]] |= vcmp.gt(v0.h,v1.h)
+; CHECK: v0 = vmux(q[[Q1E0]],v0,v1)
+define <32 x i16> @test_1e(<32 x i16> %v0, <32 x i16> %v1, <32 x i16> %v2) #0 {
+ %q0 = icmp sgt <32 x i16> %v0, %v1
+ %q1 = trunc <32 x i16> %v2 to <32 x i1>
+ %q2 = or <32 x i1> %q0, %q1
+ %t1 = select <32 x i1> %q2, <32 x i16> %v0, <32 x i16> %v1
+ ret <32 x i16> %t1
+}
+
+; CHECK-LABEL: test_1f:
+; CHECK: q[[Q1F0:[0-3]]] ^= vcmp.gt(v0.h,v1.h)
+; CHECK: v0 = vmux(q[[Q1F0]],v0,v1)
+define <32 x i16> @test_1f(<32 x i16> %v0, <32 x i16> %v1, <32 x i16> %v2) #0 {
+ %q0 = icmp sgt <32 x i16> %v0, %v1
+ %q1 = trunc <32 x i16> %v2 to <32 x i1>
+ %q2 = xor <32 x i1> %q0, %q1
+ %t1 = select <32 x i1> %q2, <32 x i16> %v0, <32 x i16> %v1
+ ret <32 x i16> %t1
+}
+
+; CHECK-LABEL: test_1g:
+; CHECK: q[[Q1G0:[0-3]]] &= vcmp.gt(v0.uh,v1.uh)
+; CHECK: v0 = vmux(q[[Q1G0]],v0,v1)
+define <32 x i16> @test_1g(<32 x i16> %v0, <32 x i16> %v1, <32 x i16> %v2) #0 {
+ %q0 = icmp ugt <32 x i16> %v0, %v1
+ %q1 = trunc <32 x i16> %v2 to <32 x i1>
+ %q2 = and <32 x i1> %q0, %q1
+ %t1 = select <32 x i1> %q2, <32 x i16> %v0, <32 x i16> %v1
+ ret <32 x i16> %t1
+}
+
+; CHECK-LABEL: test_1h:
+; CHECK: q[[Q1H0:[0-3]]] |= vcmp.gt(v0.uh,v1.uh)
+; CHECK: v0 = vmux(q[[Q1H0]],v0,v1)
+define <32 x i16> @test_1h(<32 x i16> %v0, <32 x i16> %v1, <32 x i16> %v2) #0 {
+ %q0 = icmp ugt <32 x i16> %v0, %v1
+ %q1 = trunc <32 x i16> %v2 to <32 x i1>
+ %q2 = or <32 x i1> %q0, %q1
+ %t1 = select <32 x i1> %q2, <32 x i16> %v0, <32 x i16> %v1
+ ret <32 x i16> %t1
+}
+
+; CHECK-LABEL: test_1i:
+; CHECK: q[[Q1I0:[0-3]]] ^= vcmp.gt(v0.uh,v1.uh)
+; CHECK: v0 = vmux(q[[Q1I0]],v0,v1)
+define <32 x i16> @test_1i(<32 x i16> %v0, <32 x i16> %v1, <32 x i16> %v2) #0 {
+ %q0 = icmp ugt <32 x i16> %v0, %v1
+ %q1 = trunc <32 x i16> %v2 to <32 x i1>
+ %q2 = xor <32 x i1> %q0, %q1
+ %t1 = select <32 x i1> %q2, <32 x i16> %v0, <32 x i16> %v1
+ ret <32 x i16> %t1
+}
+
; --- Word
; CHECK-LABEL: test_20:
@@ -276,4 +475,103 @@ define <16 x i32> @test_29(<16 x i32> %v
ret <16 x i32> %t1
}
+; CHECK-LABEL: test_2a:
+; CHECK: q[[Q2A0:[0-3]]] &= vcmp.eq(v0.w,v1.w)
+; CHECK: v0 = vmux(q[[Q2A0]],v0,v1)
+define <16 x i32> @test_2a(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) #0 {
+ %q0 = icmp eq <16 x i32> %v0, %v1
+ %q1 = trunc <16 x i32> %v2 to <16 x i1>
+ %q2 = and <16 x i1> %q0, %q1
+ %t1 = select <16 x i1> %q2, <16 x i32> %v0, <16 x i32> %v1
+ ret <16 x i32> %t1
+}
+
+; CHECK-LABEL: test_2b:
+; CHECK: q[[Q2B0:[0-3]]] |= vcmp.eq(v0.w,v1.w)
+; CHECK: v0 = vmux(q[[Q2B0]],v0,v1)
+define <16 x i32> @test_2b(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) #0 {
+ %q0 = icmp eq <16 x i32> %v0, %v1
+ %q1 = trunc <16 x i32> %v2 to <16 x i1>
+ %q2 = or <16 x i1> %q0, %q1
+ %t1 = select <16 x i1> %q2, <16 x i32> %v0, <16 x i32> %v1
+ ret <16 x i32> %t1
+}
+
+; CHECK-LABEL: test_2c:
+; CHECK: q[[Q2C0:[0-3]]] ^= vcmp.eq(v0.w,v1.w)
+; CHECK: v0 = vmux(q[[Q2C0]],v0,v1)
+define <16 x i32> @test_2c(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) #0 {
+ %q0 = icmp eq <16 x i32> %v0, %v1
+ %q1 = trunc <16 x i32> %v2 to <16 x i1>
+ %q2 = xor <16 x i1> %q0, %q1
+ %t1 = select <16 x i1> %q2, <16 x i32> %v0, <16 x i32> %v1
+ ret <16 x i32> %t1
+}
+
+; CHECK-LABEL: test_2d:
+; CHECK: q[[Q2D0:[0-3]]] &= vcmp.gt(v0.w,v1.w)
+; CHECK: v0 = vmux(q[[Q2D0]],v0,v1)
+define <16 x i32> @test_2d(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) #0 {
+ %q0 = icmp sgt <16 x i32> %v0, %v1
+ %q1 = trunc <16 x i32> %v2 to <16 x i1>
+ %q2 = and <16 x i1> %q0, %q1
+ %t1 = select <16 x i1> %q2, <16 x i32> %v0, <16 x i32> %v1
+ ret <16 x i32> %t1
+}
+
+; CHECK-LABEL: test_2e:
+; CHECK: q[[Q2E0:[0-3]]] |= vcmp.gt(v0.w,v1.w)
+; CHECK: v0 = vmux(q[[Q2E0]],v0,v1)
+define <16 x i32> @test_2e(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) #0 {
+ %q0 = icmp sgt <16 x i32> %v0, %v1
+ %q1 = trunc <16 x i32> %v2 to <16 x i1>
+ %q2 = or <16 x i1> %q0, %q1
+ %t1 = select <16 x i1> %q2, <16 x i32> %v0, <16 x i32> %v1
+ ret <16 x i32> %t1
+}
+
+; CHECK-LABEL: test_2f:
+; CHECK: q[[Q2F0:[0-3]]] ^= vcmp.gt(v0.w,v1.w)
+; CHECK: v0 = vmux(q[[Q2F0]],v0,v1)
+define <16 x i32> @test_2f(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) #0 {
+ %q0 = icmp sgt <16 x i32> %v0, %v1
+ %q1 = trunc <16 x i32> %v2 to <16 x i1>
+ %q2 = xor <16 x i1> %q0, %q1
+ %t1 = select <16 x i1> %q2, <16 x i32> %v0, <16 x i32> %v1
+ ret <16 x i32> %t1
+}
+
+; CHECK-LABEL: test_2g:
+; CHECK: q[[Q2G0:[0-3]]] &= vcmp.gt(v0.uw,v1.uw)
+; CHECK: v0 = vmux(q[[Q2G0]],v0,v1)
+define <16 x i32> @test_2g(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) #0 {
+ %q0 = icmp ugt <16 x i32> %v0, %v1
+ %q1 = trunc <16 x i32> %v2 to <16 x i1>
+ %q2 = and <16 x i1> %q0, %q1
+ %t1 = select <16 x i1> %q2, <16 x i32> %v0, <16 x i32> %v1
+ ret <16 x i32> %t1
+}
+
+; CHECK-LABEL: test_2h:
+; CHECK: q[[Q2H0:[0-3]]] |= vcmp.gt(v0.uw,v1.uw)
+; CHECK: v0 = vmux(q[[Q2H0]],v0,v1)
+define <16 x i32> @test_2h(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) #0 {
+ %q0 = icmp ugt <16 x i32> %v0, %v1
+ %q1 = trunc <16 x i32> %v2 to <16 x i1>
+ %q2 = or <16 x i1> %q0, %q1
+ %t1 = select <16 x i1> %q2, <16 x i32> %v0, <16 x i32> %v1
+ ret <16 x i32> %t1
+}
+
+; CHECK-LABEL: test_2i:
+; CHECK: q[[Q2I0:[0-3]]] ^= vcmp.gt(v0.uw,v1.uw)
+; CHECK: v0 = vmux(q[[Q2I0]],v0,v1)
+define <16 x i32> @test_2i(<16 x i32> %v0, <16 x i32> %v1, <16 x i32> %v2) #0 {
+ %q0 = icmp ugt <16 x i32> %v0, %v1
+ %q1 = trunc <16 x i32> %v2 to <16 x i1>
+ %q2 = xor <16 x i1> %q0, %q1
+ %t1 = select <16 x i1> %q2, <16 x i32> %v0, <16 x i32> %v1
+ ret <16 x i32> %t1
+}
+
attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvx,+hvx-length64b" }
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