[PATCH] D47178: [PowerPC] Remove the match pattern in the definition of LXSDX/STXSDX

Qing Shan Zhang via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon May 21 22:13:51 PDT 2018


steven.zhang created this revision.
steven.zhang added reviewers: nemanjai, hfinkel.
Herald added subscribers: kbarton, hiraditya.

The match pattern in the definition of LXSDX is xoaddr, which make the Pseudo instruction XFLOADf64 never selected. And XFLOADf64 will be expanded to LXSDX/LFDX post RA basing on the register pressure. To avoid the ambiguous, we need to remove the select pattern for LXSDX, just the same as what we did for LXSD. The same issue also happen for STXSDX.

This is the example to show this change:

cat a.ll
define double @_Z3foov() {
ret double 4.220000e+00
}
llc a.ll -mcpu=pwr8
cat a.s
_Z3foov: # @_Z3foov
.Lfunc_begin0:
.cfi_startproc
.Lfunc_gep0:
addis 2, 12, .TOC.-.Lfunc_gep0 at ha
addi 2, 2, .TOC.-.Lfunc_gep0 at l
.Lfunc_lep0:
.localentry	_Z3foov, .Lfunc_lep0-.Lfunc_gep0
; %bb.0:
addis 3, 2, .LCPI0_0 at toc@ha
addi 3, 3, .LCPI0_0 at toc@l
lxsdx 1, 0, 3 <----- LXSDX is selected in instruction selection phase.
blr
The right process should be, XFLOADf64--> LXSDX/LFDX --> LFDX
And I will commit another change to do the peephole for LFDX --> LFD post RA if this change is accepted.


https://reviews.llvm.org/D47178

Files:
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll
  llvm/test/CodeGen/PowerPC/branch_coalesce.ll
  llvm/test/CodeGen/PowerPC/build-vector-tests.ll
  llvm/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll
  llvm/test/CodeGen/PowerPC/float-to-int.ll
  llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
  llvm/test/CodeGen/PowerPC/i64-to-float.ll
  llvm/test/CodeGen/PowerPC/mcm-12.ll
  llvm/test/CodeGen/PowerPC/mcm-4.ll
  llvm/test/CodeGen/PowerPC/ppc64-align-long-double.ll
  llvm/test/CodeGen/PowerPC/pr30715.ll
  llvm/test/CodeGen/PowerPC/select_const.ll
  llvm/test/CodeGen/PowerPC/store_fptoi.ll
  llvm/test/CodeGen/PowerPC/swaps-le-6.ll
  llvm/test/CodeGen/PowerPC/unaligned.ll
  llvm/test/CodeGen/PowerPC/vsx_insert_extract_le.ll
  llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll

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