[llvm] r332705 - [X86][CET] Changing -fcf-protection behavior to comply with gcc (LLVM part)
Alexander Ivchenko via llvm-commits
llvm-commits at lists.llvm.org
Fri May 18 04:58:25 PDT 2018
Author: aivchenk
Date: Fri May 18 04:58:25 2018
New Revision: 332705
URL: http://llvm.org/viewvc/llvm-project?rev=332705&view=rev
Log:
[X86][CET] Changing -fcf-protection behavior to comply with gcc (LLVM part)
This patch aims to match the changes introduced in gcc by
https://gcc.gnu.org/ml/gcc-cvs/2018-04/msg00534.html. The
IBT feature definition is removed, with the IBT instructions
being freely available on all X86 targets. The shadow stack
instructions are also being made freely available, and the
use of all these CET instructions is controlled by the module
flags derived from the -fcf-protection clang option. The hasSHSTK
option remains since clang uses it to determine availability of
shadow stack instruction intrinsics, but it is no longer directly used.
Comes with a clang patch (D46881).
Patch by mike.dvoretsky
Differential Revision: https://reviews.llvm.org/D46882
Modified:
llvm/trunk/lib/Support/Host.cpp
llvm/trunk/lib/Target/X86/X86.td
llvm/trunk/lib/Target/X86/X86IndirectBranchTracking.cpp
llvm/trunk/lib/Target/X86/X86InstrControl.td
llvm/trunk/lib/Target/X86/X86InstrInfo.td
llvm/trunk/lib/Target/X86/X86InstrSystem.td
llvm/trunk/lib/Target/X86/X86Subtarget.cpp
llvm/trunk/lib/Target/X86/X86Subtarget.h
llvm/trunk/test/CodeGen/X86/indirect-branch-tracking.ll
llvm/trunk/test/CodeGen/X86/nocf_check.ll
llvm/trunk/test/CodeGen/X86/x32-cet-intrinsics.ll
llvm/trunk/test/CodeGen/X86/x64-cet-intrinsics.ll
llvm/trunk/test/Transforms/LoopVectorize/X86/pr23997.ll
Modified: llvm/trunk/lib/Support/Host.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Support/Host.cpp?rev=332705&r1=332704&r2=332705&view=diff
==============================================================================
--- llvm/trunk/lib/Support/Host.cpp (original)
+++ llvm/trunk/lib/Support/Host.cpp Fri May 18 04:58:25 2018
@@ -1264,8 +1264,6 @@ bool sys::getHostCPUFeatures(StringMap<b
Features["movdiri"] = HasLeaf7 && ((ECX >> 27) & 1);
Features["movdir64b"] = HasLeaf7 && ((ECX >> 28) & 1);
- Features["ibt"] = HasLeaf7 && ((EDX >> 20) & 1);
-
// There are two CPUID leafs which information associated with the pconfig
// instruction:
// EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th
Modified: llvm/trunk/lib/Target/X86/X86.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86.td?rev=332705&r1=332704&r2=332705&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86.td (original)
+++ llvm/trunk/lib/Target/X86/X86.td Fri May 18 04:58:25 2018
@@ -218,8 +218,6 @@ def FeatureSHA : SubtargetFeature<"s
[FeatureSSE2]>;
def FeatureSHSTK : SubtargetFeature<"shstk", "HasSHSTK", "true",
"Support CET Shadow-Stack instructions">;
-def FeatureIBT : SubtargetFeature<"ibt", "HasIBT", "true",
- "Support CET Indirect-Branch-Tracking instructions">;
def FeaturePRFCHW : SubtargetFeature<"prfchw", "HasPRFCHW", "true",
"Support PRFCHW instructions">;
def FeatureRDSEED : SubtargetFeature<"rdseed", "HasRDSEED", "true",
Modified: llvm/trunk/lib/Target/X86/X86IndirectBranchTracking.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86IndirectBranchTracking.cpp?rev=332705&r1=332704&r2=332705&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86IndirectBranchTracking.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86IndirectBranchTracking.cpp Fri May 18 04:58:25 2018
@@ -89,10 +89,6 @@ bool X86IndirectBranchTrackingPass::addE
bool X86IndirectBranchTrackingPass::runOnMachineFunction(MachineFunction &MF) {
const X86Subtarget &SubTarget = MF.getSubtarget<X86Subtarget>();
- // Make sure that the target supports IBT instruction.
- if (!SubTarget.hasIBT())
- return false;
-
// Check that the cf-protection-branch is enabled.
Metadata *isCFProtectionSupported =
MF.getMMI().getModule()->getModuleFlag("cf-protection-branch");
Modified: llvm/trunk/lib/Target/X86/X86InstrControl.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrControl.td?rev=332705&r1=332704&r2=332705&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrControl.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrControl.td Fri May 18 04:58:25 2018
@@ -141,7 +141,8 @@ let isBranch = 1, isTerminator = 1, isBa
[(brind (loadi64 addr:$dst))]>, Requires<[In64BitMode]>,
Sched<[WriteJumpLd]>;
- let isCodeGenOnly = 1, Predicates = [HasIBT] in {
+ // Non-tracking jumps for IBT, use with caution.
+ let isCodeGenOnly = 1 in {
def JMP16r_NT : I<0xFF, MRM4r, (outs), (ins GR16 : $dst), "jmp{w}\t{*}$dst",
[(X86NoTrackBrind GR16 : $dst)]>, Requires<[Not64BitMode]>,
OpSize16, Sched<[WriteJump]>, NOTRACK;
@@ -228,7 +229,8 @@ let isCall = 1 in
Requires<[Not64BitMode,FavorMemIndirectCall,NotUseRetpoline]>,
Sched<[WriteJumpLd]>;
- let isCodeGenOnly = 1, Predicates = [HasIBT] in {
+ // Non-tracking calls for IBT, use with caution.
+ let isCodeGenOnly = 1 in {
def CALL16r_NT : I<0xFF, MRM2r, (outs), (ins GR16 : $dst),
"call{w}\t{*}$dst",[(X86NoTrackCall GR16 : $dst)]>,
OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>, NOTRACK;
@@ -324,7 +326,8 @@ let isCall = 1, Uses = [RSP, SSP], Sched
Requires<[In64BitMode,FavorMemIndirectCall,
NotUseRetpoline]>;
- let isCodeGenOnly = 1, Predicates = [HasIBT] in{
+ // Non-tracking calls for IBT, use with caution.
+ let isCodeGenOnly = 1 in {
def CALL64r_NT : I<0xFF, MRM2r, (outs), (ins GR64 : $dst),
"call{q}\t{*}$dst",[(X86NoTrackCall GR64 : $dst)]>,
Requires<[In64BitMode]>, NOTRACK;
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.td?rev=332705&r1=332704&r2=332705&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.td Fri May 18 04:58:25 2018
@@ -899,7 +899,6 @@ def FPStackf32 : Predicate<"!Subtarget
def FPStackf64 : Predicate<"!Subtarget->hasSSE2()">;
def HasMPX : Predicate<"Subtarget->hasMPX()">;
def HasSHSTK : Predicate<"Subtarget->hasSHSTK()">;
-def HasIBT : Predicate<"Subtarget->hasIBT()">;
def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">;
def HasCLWB : Predicate<"Subtarget->hasCLWB()">;
def HasWBNOINVD : Predicate<"Subtarget->hasWBNOINVD()">;
Modified: llvm/trunk/lib/Target/X86/X86InstrSystem.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrSystem.td?rev=332705&r1=332704&r2=332705&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrSystem.td (original)
+++ llvm/trunk/lib/Target/X86/X86InstrSystem.td Fri May 18 04:58:25 2018
@@ -450,7 +450,8 @@ def WBNOINVD : I<0x09, RawFrm, (outs), (
//===----------------------------------------------------------------------===//
// CET instructions
-let SchedRW = [WriteSystem], Predicates = [HasSHSTK] in{
+// Use with caution, availability is not predicated on features.
+let SchedRW = [WriteSystem] in {
let Uses = [SSP] in {
let Defs = [SSP] in {
def INCSSPD : I<0xAE, MRM5r, (outs), (ins GR32:$src), "incsspd\t$src",
@@ -500,12 +501,12 @@ let SchedRW = [WriteSystem], Predicates
"clrssbsy\t$src",
[(int_x86_clrssbsy addr:$src)]>, XS;
} // Defs SSP
-} // SchedRW && HasSHSTK
+} // SchedRW
-let SchedRW = [WriteSystem], Predicates = [HasIBT] in {
+let SchedRW = [WriteSystem] in {
def ENDBR64 : I<0x1E, MRM_FA, (outs), (ins), "endbr64", []>, XS;
def ENDBR32 : I<0x1E, MRM_FB, (outs), (ins), "endbr32", []>, XS;
-} // SchedRW && HasIBT
+} // SchedRW
//===----------------------------------------------------------------------===//
// XSAVE instructions
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.cpp?rev=332705&r1=332704&r2=332705&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.cpp Fri May 18 04:58:25 2018
@@ -322,7 +322,6 @@ void X86Subtarget::initializeEnvironment
HasPTWRITE = false;
HasMPX = false;
HasSHSTK = false;
- HasIBT = false;
HasSGX = false;
HasPCONFIG = false;
HasCLFLUSHOPT = false;
Modified: llvm/trunk/lib/Target/X86/X86Subtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86Subtarget.h?rev=332705&r1=332704&r2=332705&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86Subtarget.h (original)
+++ llvm/trunk/lib/Target/X86/X86Subtarget.h Fri May 18 04:58:25 2018
@@ -360,10 +360,6 @@ protected:
/// using Shadow Stack
bool HasSHSTK;
- /// Processor supports CET IBT - Control-Flow Enforcement Technology
- /// using Indirect Branch Tracking
- bool HasIBT;
-
/// Processor has Software Guard Extensions
bool HasSGX;
@@ -641,7 +637,6 @@ public:
bool hasBITALG() const { return HasBITALG; }
bool hasMPX() const { return HasMPX; }
bool hasSHSTK() const { return HasSHSTK; }
- bool hasIBT() const { return HasIBT; }
bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
bool hasCLWB() const { return HasCLWB; }
bool hasWBNOINVD() const { return HasWBNOINVD; }
Modified: llvm/trunk/test/CodeGen/X86/indirect-branch-tracking.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/indirect-branch-tracking.ll?rev=332705&r1=332704&r2=332705&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/indirect-branch-tracking.ll (original)
+++ llvm/trunk/test/CodeGen/X86/indirect-branch-tracking.ll Fri May 18 04:58:25 2018
@@ -1,6 +1,6 @@
-; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+ibt < %s | FileCheck %s --check-prefix=ALL --check-prefix=X86_64
-; RUN: llc -mtriple=i386-unknown-unknown -mattr=+ibt < %s | FileCheck %s --check-prefix=ALL --check-prefix=X86
-; RUN: llc -mtriple i386-windows-gnu -mattr=+ibt -exception-model sjlj < %s | FileCheck %s --check-prefix=SJLJ
+; RUN: llc -mtriple=x86_64-unknown-unknown < %s | FileCheck %s --check-prefix=ALL --check-prefix=X86_64
+; RUN: llc -mtriple=i386-unknown-unknown < %s | FileCheck %s --check-prefix=ALL --check-prefix=X86
+; RUN: llc -mtriple i386-windows-gnu -exception-model sjlj < %s | FileCheck %s --check-prefix=SJLJ
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; Test1
@@ -218,4 +218,4 @@ try.cont:
!llvm.module.flags = !{!0}
-!0 = !{i32 4, !"cf-protection-branch", i32 1}
\ No newline at end of file
+!0 = !{i32 4, !"cf-protection-branch", i32 1}
Modified: llvm/trunk/test/CodeGen/X86/nocf_check.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/nocf_check.ll?rev=332705&r1=332704&r2=332705&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/nocf_check.ll (original)
+++ llvm/trunk/test/CodeGen/X86/nocf_check.ll Fri May 18 04:58:25 2018
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=+ibt -x86-indirect-branch-tracking < %s | FileCheck %s
+; RUN: llc -mtriple=x86_64-unknown-unknown -x86-indirect-branch-tracking < %s | FileCheck %s
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;; This test verify the handling of ''nocf_check'' attribute by the backend. ;;
Modified: llvm/trunk/test/CodeGen/X86/x32-cet-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x32-cet-intrinsics.ll?rev=332705&r1=332704&r2=332705&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/x32-cet-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/x32-cet-intrinsics.ll Fri May 18 04:58:25 2018
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+shstk -mattr=+ibt | FileCheck %s
+; RUN: llc < %s -mtriple=i386-apple-darwin -mattr=+shstk | FileCheck %s
define void @test_incsspd(i32 %a) local_unnamed_addr {
; CHECK-LABEL: test_incsspd:
Modified: llvm/trunk/test/CodeGen/X86/x64-cet-intrinsics.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/x64-cet-intrinsics.ll?rev=332705&r1=332704&r2=332705&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/x64-cet-intrinsics.ll (original)
+++ llvm/trunk/test/CodeGen/X86/x64-cet-intrinsics.ll Fri May 18 04:58:25 2018
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+shstk -mattr=+ibt | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -mattr=+shstk | FileCheck %s
define void @test_incsspd(i32 %a) local_unnamed_addr {
; CHECK-LABEL: test_incsspd:
Modified: llvm/trunk/test/Transforms/LoopVectorize/X86/pr23997.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/Transforms/LoopVectorize/X86/pr23997.ll?rev=332705&r1=332704&r2=332705&view=diff
==============================================================================
--- llvm/trunk/test/Transforms/LoopVectorize/X86/pr23997.ll (original)
+++ llvm/trunk/test/Transforms/LoopVectorize/X86/pr23997.ll Fri May 18 04:58:25 2018
@@ -103,7 +103,7 @@ loopexit:
ret void
}
-attributes #0 = { uwtable "target-cpu"="skylake" "target-features"="+sse2,+cx16,+sahf,-tbm,-avx512ifma,-sha,-gfni,-fma4,-vpclmulqdq,+prfchw,+bmi2,-cldemote,+fsgsbase,+xsavec,+popcnt,+aes,-avx512bitalg,+xsaves,-avx512er,-avx512vnni,-avx512vpopcntdq,-clwb,-avx512f,-clzero,-pku,+mmx,-lwp,-rdpid,-xop,+rdseed,-waitpkg,-ibt,-sse4a,-avx512bw,+clflushopt,+xsave,-avx512vbmi2,-avx512vl,-avx512cd,+avx,-vaes,+rtm,+fma,+bmi,+rdrnd,-mwaitx,+sse4.1,+sse4.2,+avx2,-wbnoinvd,+sse,+lzcnt,+pclmul,-prefetchwt1,+f16c,+ssse3,+sgx,-shstk,+cmov,-avx512vbmi,+movbe,+xsaveopt,-avx512dq,+adx,-avx512pf,+sse3" }
+attributes #0 = { uwtable "target-cpu"="skylake" "target-features"="+sse2,+cx16,+sahf,-tbm,-avx512ifma,-sha,-gfni,-fma4,-vpclmulqdq,+prfchw,+bmi2,-cldemote,+fsgsbase,+xsavec,+popcnt,+aes,-avx512bitalg,+xsaves,-avx512er,-avx512vnni,-avx512vpopcntdq,-clwb,-avx512f,-clzero,-pku,+mmx,-lwp,-rdpid,-xop,+rdseed,-waitpkg,-sse4a,-avx512bw,+clflushopt,+xsave,-avx512vbmi2,-avx512vl,-avx512cd,+avx,-vaes,+rtm,+fma,+bmi,+rdrnd,-mwaitx,+sse4.1,+sse4.2,+avx2,-wbnoinvd,+sse,+lzcnt,+pclmul,-prefetchwt1,+f16c,+ssse3,+sgx,-shstk,+cmov,-avx512vbmi,+movbe,+xsaveopt,-avx512dq,+adx,-avx512pf,+sse3" }
!0 = !{i32 0, i32 2147483646}
!1 = !{}
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