[PATCH] D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes.

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: include/llvm/Target/TargetInstrPredicate.td:110
+// operand at position `Index` is a register operand.
+class CheckRegOperandValue<int Index, Register R>
+    : MCOperandPredicate<Index> {
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The use of 'Value' makes is it sound like we need the register to contain a certain value, not that it must be a certain register.


https://reviews.llvm.org/D46695