[llvm] r332641 - [RISCV] Separate base from offset in lowerGlobalAddress
Sameer AbuAsal via llvm-commits
llvm-commits at lists.llvm.org
Thu May 17 11:14:53 PDT 2018
Author: sabuasal
Date: Thu May 17 11:14:53 2018
New Revision: 332641
URL: http://llvm.org/viewvc/llvm-project?rev=332641&view=rev
Log:
[RISCV] Separate base from offset in lowerGlobalAddress
Summary:
When lowering global address, lower the base as a TargetGlobal first then
create an SDNode for the offset separately and chain it to the address calculation
This optimization will create a DAG where the base address of a global access will
be reused between different access. The offset can later be folded into the immediate
part of the memory access instruction.
With this optimization we generate:
lui a0, %hi(s)
addi a0, a0, %lo(s) ; shared base address.
addi a1, zero, 20 ; 2 instructions per access.
sw a1, 44(a0)
addi a1, zero, 10
sw a1, 8(a0)
addi a1, zero, 30
sw a1, 80(a0)
Instead of:
lui a0, %hi(s+44) ; 3 instructions per access.
addi a1, zero, 20
sw a1, %lo(s+44)(a0)
lui a0, %hi(s+8)
addi a1, zero, 10
sw a1, %lo(s+8)(a0)
lui a0, %hi(s+80)
addi a1, zero, 30
sw a1, %lo(s+80)(a0)
Which will save one instruction per access.
Reviewers: asb, apazos
Reviewed By: asb
Subscribers: rbar, johnrusso, simoncook, jordy.potman.lists, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, mgrang, apazos, asb, llvm-commits
Differential Revision: https://reviews.llvm.org/D46989
Added:
llvm/trunk/test/CodeGen/RISCV/hoist-global-addr-base.ll
Modified:
llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/trunk/test/CodeGen/RISCV/byval.ll
llvm/trunk/test/CodeGen/RISCV/double-mem.ll
llvm/trunk/test/CodeGen/RISCV/float-mem.ll
llvm/trunk/test/CodeGen/RISCV/fp128.ll
llvm/trunk/test/CodeGen/RISCV/mem.ll
llvm/trunk/test/CodeGen/RISCV/wide-mem.ll
llvm/trunk/test/CodeGen/RISCV/zext-with-load-is-free.ll
Modified: llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp?rev=332641&r1=332640&r2=332641&view=diff
==============================================================================
--- llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/RISCV/RISCVISelLowering.cpp Thu May 17 11:14:53 2018
@@ -293,17 +293,22 @@ SDValue RISCVTargetLowering::lowerGlobal
GlobalAddressSDNode *N = cast<GlobalAddressSDNode>(Op);
const GlobalValue *GV = N->getGlobal();
int64_t Offset = N->getOffset();
+ MVT XLenVT = Subtarget.getXLenVT();
if (isPositionIndependent() || Subtarget.is64Bit())
report_fatal_error("Unable to lowerGlobalAddress");
-
- SDValue GAHi =
- DAG.getTargetGlobalAddress(GV, DL, Ty, Offset, RISCVII::MO_HI);
- SDValue GALo =
- DAG.getTargetGlobalAddress(GV, DL, Ty, Offset, RISCVII::MO_LO);
+ // In order to maximise the opportunity for common subexpression elimination,
+ // emit a separate ADD node for the global address offset instead of folding
+ // it in the global address node. Later peephole optimisations may choose to
+ // fold it back in when profitable.
+ SDValue GAHi = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, RISCVII::MO_HI);
+ SDValue GALo = DAG.getTargetGlobalAddress(GV, DL, Ty, 0, RISCVII::MO_LO);
SDValue MNHi = SDValue(DAG.getMachineNode(RISCV::LUI, DL, Ty, GAHi), 0);
SDValue MNLo =
SDValue(DAG.getMachineNode(RISCV::ADDI, DL, Ty, MNHi, GALo), 0);
+ if (Offset != 0)
+ return DAG.getNode(ISD::ADD, DL, Ty, MNLo,
+ DAG.getConstant(Offset, DL, XLenVT));
return MNLo;
}
Modified: llvm/trunk/test/CodeGen/RISCV/byval.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/byval.ll?rev=332641&r1=332640&r2=332641&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/byval.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/byval.ll Thu May 17 11:14:53 2018
@@ -22,18 +22,16 @@ define void @caller() nounwind {
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: addi sp, sp, -32
; RV32I-NEXT: sw ra, 28(sp)
-; RV32I-NEXT: lui a0, %hi(foo+12)
-; RV32I-NEXT: lw a0, %lo(foo+12)(a0)
-; RV32I-NEXT: sw a0, 24(sp)
-; RV32I-NEXT: lui a0, %hi(foo+8)
-; RV32I-NEXT: lw a0, %lo(foo+8)(a0)
-; RV32I-NEXT: sw a0, 20(sp)
-; RV32I-NEXT: lui a0, %hi(foo+4)
-; RV32I-NEXT: lw a0, %lo(foo+4)(a0)
-; RV32I-NEXT: sw a0, 16(sp)
; RV32I-NEXT: lui a0, %hi(foo)
-; RV32I-NEXT: lw a0, %lo(foo)(a0)
-; RV32I-NEXT: sw a0, 12(sp)
+; RV32I-NEXT: lw a1, %lo(foo)(a0)
+; RV32I-NEXT: sw a1, 12(sp)
+; RV32I-NEXT: addi a0, a0, %lo(foo)
+; RV32I-NEXT: lw a1, 12(a0)
+; RV32I-NEXT: sw a1, 24(sp)
+; RV32I-NEXT: lw a1, 8(a0)
+; RV32I-NEXT: sw a1, 20(sp)
+; RV32I-NEXT: lw a0, 4(a0)
+; RV32I-NEXT: sw a0, 16(sp)
; RV32I-NEXT: addi a0, sp, 12
; RV32I-NEXT: call callee
; RV32I-NEXT: lw ra, 28(sp)
Modified: llvm/trunk/test/CodeGen/RISCV/double-mem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/double-mem.ll?rev=332641&r1=332640&r2=332641&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/double-mem.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/double-mem.ll Thu May 17 11:14:53 2018
@@ -64,9 +64,9 @@ define double @fld_fsd_global(double %a,
; RV32IFD-NEXT: lui a0, %hi(G)
; RV32IFD-NEXT: fld ft1, %lo(G)(a0)
; RV32IFD-NEXT: fsd ft0, %lo(G)(a0)
-; RV32IFD-NEXT: lui a0, %hi(G+72)
-; RV32IFD-NEXT: fld ft1, %lo(G+72)(a0)
-; RV32IFD-NEXT: fsd ft0, %lo(G+72)(a0)
+; RV32IFD-NEXT: addi a0, a0, %lo(G)
+; RV32IFD-NEXT: fld ft1, 72(a0)
+; RV32IFD-NEXT: fsd ft0, 72(a0)
; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp)
Modified: llvm/trunk/test/CodeGen/RISCV/float-mem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/float-mem.ll?rev=332641&r1=332640&r2=332641&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/float-mem.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/float-mem.ll Thu May 17 11:14:53 2018
@@ -51,9 +51,9 @@ define float @flw_fsw_global(float %a, f
; RV32IF-NEXT: lui a0, %hi(G)
; RV32IF-NEXT: flw ft1, %lo(G)(a0)
; RV32IF-NEXT: fsw ft0, %lo(G)(a0)
-; RV32IF-NEXT: lui a0, %hi(G+36)
-; RV32IF-NEXT: flw ft1, %lo(G+36)(a0)
-; RV32IF-NEXT: fsw ft0, %lo(G+36)(a0)
+; RV32IF-NEXT: addi a0, a0, %lo(G)
+; RV32IF-NEXT: flw ft1, 36(a0)
+; RV32IF-NEXT: fsw ft0, 36(a0)
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
%1 = fadd float %a, %b
Modified: llvm/trunk/test/CodeGen/RISCV/fp128.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/fp128.ll?rev=332641&r1=332640&r2=332641&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/fp128.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/fp128.ll Thu May 17 11:14:53 2018
@@ -13,30 +13,26 @@ define i32 @test_load_and_cmp() nounwind
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -48
; RV32I-NEXT: sw ra, 44(sp)
-; RV32I-NEXT: lui a0, %hi(y+12)
-; RV32I-NEXT: lw a0, %lo(y+12)(a0)
-; RV32I-NEXT: sw a0, 20(sp)
-; RV32I-NEXT: lui a0, %hi(y+8)
-; RV32I-NEXT: lw a0, %lo(y+8)(a0)
-; RV32I-NEXT: sw a0, 16(sp)
-; RV32I-NEXT: lui a0, %hi(y+4)
-; RV32I-NEXT: lw a0, %lo(y+4)(a0)
-; RV32I-NEXT: sw a0, 12(sp)
; RV32I-NEXT: lui a0, %hi(y)
-; RV32I-NEXT: lw a0, %lo(y)(a0)
-; RV32I-NEXT: sw a0, 8(sp)
-; RV32I-NEXT: lui a0, %hi(x+12)
-; RV32I-NEXT: lw a0, %lo(x+12)(a0)
-; RV32I-NEXT: sw a0, 36(sp)
-; RV32I-NEXT: lui a0, %hi(x+8)
-; RV32I-NEXT: lw a0, %lo(x+8)(a0)
-; RV32I-NEXT: sw a0, 32(sp)
-; RV32I-NEXT: lui a0, %hi(x+4)
-; RV32I-NEXT: lw a0, %lo(x+4)(a0)
+; RV32I-NEXT: lw a1, %lo(y)(a0)
+; RV32I-NEXT: sw a1, 8(sp)
+; RV32I-NEXT: lui a1, %hi(x)
+; RV32I-NEXT: lw a2, %lo(x)(a1)
+; RV32I-NEXT: sw a2, 24(sp)
+; RV32I-NEXT: addi a0, a0, %lo(y)
+; RV32I-NEXT: lw a2, 12(a0)
+; RV32I-NEXT: sw a2, 20(sp)
+; RV32I-NEXT: lw a2, 8(a0)
+; RV32I-NEXT: sw a2, 16(sp)
+; RV32I-NEXT: lw a0, 4(a0)
+; RV32I-NEXT: sw a0, 12(sp)
+; RV32I-NEXT: addi a0, a1, %lo(x)
+; RV32I-NEXT: lw a1, 12(a0)
+; RV32I-NEXT: sw a1, 36(sp)
+; RV32I-NEXT: lw a1, 8(a0)
+; RV32I-NEXT: sw a1, 32(sp)
+; RV32I-NEXT: lw a0, 4(a0)
; RV32I-NEXT: sw a0, 28(sp)
-; RV32I-NEXT: lui a0, %hi(x)
-; RV32I-NEXT: lw a0, %lo(x)(a0)
-; RV32I-NEXT: sw a0, 24(sp)
; RV32I-NEXT: addi a0, sp, 24
; RV32I-NEXT: addi a1, sp, 8
; RV32I-NEXT: call __netf2
@@ -57,30 +53,26 @@ define i32 @test_add_and_fptosi() nounwi
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -80
; RV32I-NEXT: sw ra, 76(sp)
-; RV32I-NEXT: lui a0, %hi(y+12)
-; RV32I-NEXT: lw a0, %lo(y+12)(a0)
-; RV32I-NEXT: sw a0, 36(sp)
-; RV32I-NEXT: lui a0, %hi(y+8)
-; RV32I-NEXT: lw a0, %lo(y+8)(a0)
-; RV32I-NEXT: sw a0, 32(sp)
-; RV32I-NEXT: lui a0, %hi(y+4)
-; RV32I-NEXT: lw a0, %lo(y+4)(a0)
-; RV32I-NEXT: sw a0, 28(sp)
; RV32I-NEXT: lui a0, %hi(y)
-; RV32I-NEXT: lw a0, %lo(y)(a0)
-; RV32I-NEXT: sw a0, 24(sp)
-; RV32I-NEXT: lui a0, %hi(x+12)
-; RV32I-NEXT: lw a0, %lo(x+12)(a0)
-; RV32I-NEXT: sw a0, 52(sp)
-; RV32I-NEXT: lui a0, %hi(x+8)
-; RV32I-NEXT: lw a0, %lo(x+8)(a0)
-; RV32I-NEXT: sw a0, 48(sp)
-; RV32I-NEXT: lui a0, %hi(x+4)
-; RV32I-NEXT: lw a0, %lo(x+4)(a0)
+; RV32I-NEXT: lw a1, %lo(y)(a0)
+; RV32I-NEXT: sw a1, 24(sp)
+; RV32I-NEXT: lui a1, %hi(x)
+; RV32I-NEXT: lw a2, %lo(x)(a1)
+; RV32I-NEXT: sw a2, 40(sp)
+; RV32I-NEXT: addi a0, a0, %lo(y)
+; RV32I-NEXT: lw a2, 12(a0)
+; RV32I-NEXT: sw a2, 36(sp)
+; RV32I-NEXT: lw a2, 8(a0)
+; RV32I-NEXT: sw a2, 32(sp)
+; RV32I-NEXT: lw a0, 4(a0)
+; RV32I-NEXT: sw a0, 28(sp)
+; RV32I-NEXT: addi a0, a1, %lo(x)
+; RV32I-NEXT: lw a1, 12(a0)
+; RV32I-NEXT: sw a1, 52(sp)
+; RV32I-NEXT: lw a1, 8(a0)
+; RV32I-NEXT: sw a1, 48(sp)
+; RV32I-NEXT: lw a0, 4(a0)
; RV32I-NEXT: sw a0, 44(sp)
-; RV32I-NEXT: lui a0, %hi(x)
-; RV32I-NEXT: lw a0, %lo(x)(a0)
-; RV32I-NEXT: sw a0, 40(sp)
; RV32I-NEXT: addi a0, sp, 56
; RV32I-NEXT: addi a1, sp, 40
; RV32I-NEXT: addi a2, sp, 24
Added: llvm/trunk/test/CodeGen/RISCV/hoist-global-addr-base.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/hoist-global-addr-base.ll?rev=332641&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/hoist-global-addr-base.ll (added)
+++ llvm/trunk/test/CodeGen/RISCV/hoist-global-addr-base.ll Thu May 17 11:14:53 2018
@@ -0,0 +1,111 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s
+
+%struct.S = type { [40 x i32], i32, i32, i32, [4100 x i32], i32, i32, i32 }
+ at s = common dso_local global %struct.S zeroinitializer, align 4
+ at foo = global [6 x i16] [i16 1, i16 2, i16 3, i16 4, i16 5, i16 0], align 2
+
+define dso_local void @multiple_stores() local_unnamed_addr {
+; CHECK-LABEL: multiple_stores:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lui a0, %hi(s)
+; CHECK-NEXT: addi a0, a0, %lo(s)
+; CHECK-NEXT: addi a1, zero, 20
+; CHECK-NEXT: sw a1, 164(a0)
+; CHECK-NEXT: addi a1, zero, 10
+; CHECK-NEXT: sw a1, 160(a0)
+; CHECK-NEXT: ret
+entry:
+ store i32 10, i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 1), align 4
+ store i32 20, i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 2), align 4
+ ret void
+}
+
+define dso_local void @control_flow() local_unnamed_addr #0 {
+; CHECK-LABEL: control_flow:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lui a0, %hi(s)
+; CHECK-NEXT: addi a0, a0, %lo(s)
+; CHECK-NEXT: lw a1, 164(a0)
+; CHECK-NEXT: addi a2, zero, 1
+; CHECK-NEXT: blt a1, a2, .LBB1_2
+; CHECK-NEXT: # %bb.1: # %if.then
+; CHECK-NEXT: addi a1, zero, 10
+; CHECK-NEXT: sw a1, 160(a0)
+; CHECK-NEXT: .LBB1_2: # %if.end
+; CHECK-NEXT: ret
+entry:
+ %0 = load i32, i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 2), align 4
+ %cmp = icmp sgt i32 %0, 0
+ br i1 %cmp, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ store i32 10, i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 1), align 4
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ ret void
+}
+
+;TODO: Offset shouln't be separated in this case. We get shorter sequence if it
+; is merged in the LUI %hi and the ADDI %lo.
+define dso_local i32* @big_offset_one_use() local_unnamed_addr {
+; CHECK-LABEL: big_offset_one_use:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lui a0, 4
+; CHECK-NEXT: addi a0, a0, 188
+; CHECK-NEXT: lui a1, %hi(s)
+; CHECK-NEXT: addi a1, a1, %lo(s)
+; CHECK-NEXT: add a0, a1, a0
+; CHECK-NEXT: ret
+entry:
+ ret i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 5)
+}
+
+;TODO: Offset shouln't be separated in this case. We get shorter sequence if it
+; is merged in the LUI %hi and the ADDI %lo.
+define dso_local i32* @small_offset_one_use() local_unnamed_addr {
+; CHECK-LABEL: small_offset_one_use:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lui a0, %hi(s)
+; CHECK-NEXT: addi a0, a0, %lo(s)
+; CHECK-NEXT: addi a0, a0, 160
+; CHECK-NEXT: ret
+entry:
+ ret i32* getelementptr inbounds (%struct.S, %struct.S* @s, i32 0, i32 1)
+}
+
+
+;TODO: Offset shouln't be separated in this case. We get shorter sequence if it
+; is merged in the LUI %hi and the ADDI %lo.
+define dso_local i32 @load_half() nounwind {
+; CHECK-LABEL: load_half:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: addi sp, sp, -16
+; CHECK-NEXT: sw ra, 12(sp)
+; CHECK-NEXT: lui a0, %hi(foo)
+; CHECK-NEXT: addi a0, a0, %lo(foo)
+; CHECK-NEXT: lhu a0, 8(a0)
+; CHECK-NEXT: addi a1, zero, 140
+; CHECK-NEXT: bne a0, a1, .LBB4_2
+; CHECK-NEXT: # %bb.1: # %if.end
+; CHECK-NEXT: mv a0, zero
+; CHECK-NEXT: lw ra, 12(sp)
+; CHECK-NEXT: addi sp, sp, 16
+; CHECK-NEXT: ret
+; CHECK-NEXT: .LBB4_2: # %if.then
+; CHECK-NEXT: call abort
+entry:
+ %0 = load i16, i16* getelementptr inbounds ([6 x i16], [6 x i16]* @foo, i32 0, i32 4), align 2
+ %cmp = icmp eq i16 %0, 140
+ br i1 %cmp, label %if.end, label %if.then
+
+if.then:
+ tail call void @abort()
+ unreachable
+
+if.end:
+ ret i32 0
+}
+
+declare void @abort()
Modified: llvm/trunk/test/CodeGen/RISCV/mem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/mem.ll?rev=332641&r1=332640&r2=332641&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/mem.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/mem.ll Thu May 17 11:14:53 2018
@@ -168,9 +168,9 @@ define i32 @lw_sw_global(i32 %a) nounwin
; RV32I-NEXT: lui a2, %hi(G)
; RV32I-NEXT: lw a1, %lo(G)(a2)
; RV32I-NEXT: sw a0, %lo(G)(a2)
-; RV32I-NEXT: lui a2, %hi(G+36)
-; RV32I-NEXT: lw a3, %lo(G+36)(a2)
-; RV32I-NEXT: sw a0, %lo(G+36)(a2)
+; RV32I-NEXT: addi a2, a2, %lo(G)
+; RV32I-NEXT: lw a3, 36(a2)
+; RV32I-NEXT: sw a0, 36(a2)
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: ret
%1 = load volatile i32, i32* @G
Modified: llvm/trunk/test/CodeGen/RISCV/wide-mem.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/wide-mem.ll?rev=332641&r1=332640&r2=332641&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/wide-mem.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/wide-mem.ll Thu May 17 11:14:53 2018
@@ -20,10 +20,10 @@ define i64 @load_i64(i64 *%a) nounwind {
define i64 @load_i64_global() nounwind {
; RV32I-LABEL: load_i64_global:
; RV32I: # %bb.0:
-; RV32I-NEXT: lui a0, %hi(val64)
-; RV32I-NEXT: lw a0, %lo(val64)(a0)
-; RV32I-NEXT: lui a1, %hi(val64+4)
-; RV32I-NEXT: lw a1, %lo(val64+4)(a1)
+; RV32I-NEXT: lui a1, %hi(val64)
+; RV32I-NEXT: lw a0, %lo(val64)(a1)
+; RV32I-NEXT: addi a1, a1, %lo(val64)
+; RV32I-NEXT: lw a1, 4(a1)
; RV32I-NEXT: ret
%1 = load i64, i64* @val64
ret i64 %1
Modified: llvm/trunk/test/CodeGen/RISCV/zext-with-load-is-free.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/RISCV/zext-with-load-is-free.ll?rev=332641&r1=332640&r2=332641&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/RISCV/zext-with-load-is-free.ll (original)
+++ llvm/trunk/test/CodeGen/RISCV/zext-with-load-is-free.ll Thu May 17 11:14:53 2018
@@ -10,12 +10,12 @@ define i32 @test_zext_i8() {
; RV32I-LABEL: test_zext_i8:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a0, %hi(bytes)
-; RV32I-NEXT: lbu a0, %lo(bytes)(a0)
-; RV32I-NEXT: addi a1, zero, 136
-; RV32I-NEXT: bne a0, a1, .LBB0_3
+; RV32I-NEXT: lbu a1, %lo(bytes)(a0)
+; RV32I-NEXT: addi a2, zero, 136
+; RV32I-NEXT: bne a1, a2, .LBB0_3
; RV32I-NEXT: # %bb.1: # %entry
-; RV32I-NEXT: lui a0, %hi(bytes+1)
-; RV32I-NEXT: lbu a0, %lo(bytes+1)(a0)
+; RV32I-NEXT: addi a0, a0, %lo(bytes)
+; RV32I-NEXT: lbu a0, 1(a0)
; RV32I-NEXT: addi a1, zero, 7
; RV32I-NEXT: bne a0, a1, .LBB0_3
; RV32I-NEXT: # %bb.2: # %if.end
@@ -44,14 +44,14 @@ if.end:
define i32 @test_zext_i16() {
; RV32I-LABEL: test_zext_i16:
; RV32I: # %bb.0: # %entry
-; RV32I-NEXT: lui a0, 16
-; RV32I-NEXT: addi a0, a0, -120
-; RV32I-NEXT: lui a1, %hi(shorts)
-; RV32I-NEXT: lhu a1, %lo(shorts)(a1)
-; RV32I-NEXT: bne a1, a0, .LBB1_3
+; RV32I-NEXT: lui a0, %hi(shorts)
+; RV32I-NEXT: lui a1, 16
+; RV32I-NEXT: addi a1, a1, -120
+; RV32I-NEXT: lhu a2, %lo(shorts)(a0)
+; RV32I-NEXT: bne a2, a1, .LBB1_3
; RV32I-NEXT: # %bb.1: # %entry
-; RV32I-NEXT: lui a0, %hi(shorts+2)
-; RV32I-NEXT: lhu a0, %lo(shorts+2)(a0)
+; RV32I-NEXT: addi a0, a0, %lo(shorts)
+; RV32I-NEXT: lhu a0, 2(a0)
; RV32I-NEXT: addi a1, zero, 7
; RV32I-NEXT: bne a0, a1, .LBB1_3
; RV32I-NEXT: # %bb.2: # %if.end
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