[llvm] r332591 - [X86][SNB] Minor scheduler cleanup

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Thu May 17 03:36:29 2018
New Revision: 332591

URL: http://llvm.org/viewvc/llvm-project?rev=332591&view=rev
Log:
[X86][SNB] Minor scheduler cleanup

Merge 2 instregex and explain the VMOVDQArr/MOVDQArr difference

Modified:
    llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td

Modified: llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td?rev=332591&r1=332590&r2=332591&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td (original)
+++ llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td Thu May 17 03:36:29 2018
@@ -512,9 +512,7 @@ def: InstRW<[SBWriteResGroup4], (instreg
                                            "BTR(16|32|64)ri8",
                                            "BTR(16|32|64)rr",
                                            "BTS(16|32|64)ri8",
-                                           "BTS(16|32|64)rr",
-                                           "VMOVDQA(Y?)rr",
-                                           "VMOVDQU(Y?)rr")>;
+                                           "BTS(16|32|64)rr")>;
 
 def SBWriteResGroup5 : SchedWriteRes<[SBPort15]> {
   let Latency = 1;
@@ -532,8 +530,7 @@ def SBWriteResGroup6 : SchedWriteRes<[SB
   let ResourceCycles = [1];
 }
 def: InstRW<[SBWriteResGroup6], (instregex "MMX_MOVQ2DQrr",
-                                           "MOVDQArr", // TODO: Why are these separated from their VEX equivalent
-                                           "MOVDQUrr")>; // TODO: Why are these separated from their VEX equivalent
+                                           "MOVDQ(A|U)rr")>; // NOTE: Different port requirements to VEX equivalents
 
 def SBWriteResGroup7 : SchedWriteRes<[SBPort0]> {
   let Latency = 2;
@@ -743,8 +740,7 @@ def SBWriteResGroup33 : SchedWriteRes<[S
   let NumMicroOps = 2;
   let ResourceCycles = [1,1];
 }
-def: InstRW<[SBWriteResGroup33], (instregex "PUSH64i8",
-                                            "PUSH(16|32|64)r")>;
+def: InstRW<[SBWriteResGroup33], (instregex "PUSH(16r|32r|64r|64i8)")>;
 
 def SBWriteResGroup35 : SchedWriteRes<[SBPort1,SBPort5]> {
   let Latency = 5;