[PATCH] D46959: [X86][SSE] Reduce instruction/register usages for v4i32 vector shifts (PR37441)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added inline comments.


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Comment at: lib/Target/X86/X86ISelLowering.cpp:23447
+
+    SDValue R0 = DAG.getNode(Opc, dl, VT, R, DAG.getBitcast(VT, Amt0));
+    SDValue R1 = DAG.getNode(Opc, dl, VT, R, DAG.getBitcast(VT, Amt1));
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craig.topper wrote:
> Are these bitcasts here because you could fold them into this line? They are only needed on the non-AVX path from above right?
Yes, I was cheating and saving space, wrapping them around the non-AVX getVectorShuffle isn't pretty either.


Repository:
  rL LLVM

https://reviews.llvm.org/D46959