[PATCH] D46959: [X86][SSE] Reduce instruction/register usages for v4i32 vector shifts (PR37441)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: spatel, craig.topper, andreadb.

As suggested by Fabian on PR37441, use PSHUFLW to extend shift amount types for use with PSRAD/PSRLD to reduce register pressure.

Some of this ideally would be done by combineTargetShuffle but its tricky to do as most of the shuffles are sharing inputs.


Repository:
  rL LLVM

https://reviews.llvm.org/D46959

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/combine-sra.ll
  test/CodeGen/X86/combine-srl.ll
  test/CodeGen/X86/combine-udiv.ll
  test/CodeGen/X86/combine-urem.ll
  test/CodeGen/X86/vector-rotate-128.ll
  test/CodeGen/X86/vector-shift-ashr-128.ll
  test/CodeGen/X86/vector-shift-lshr-128.ll

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