[PATCH] D45395: [RISCV] Lower the tail pseudoinstruction

[Mandeep Singh Grang via Phabricator via llvm-commits]

mgrang added a comment.

Thanks for the comments Alex. I had a couple of observations:

1. For PseudoTAILIndirect if I do not specify an AsmString then I don't see any instruction in the generated assembly. Is this because PseudoTAILIndirect is lowered in the RISCVMCCodeEmitter.cpp and may be too late for the assembly generation? What do you suggest to counter this?

2. I am not sure if we need the pattern for texternalsym:

  def : Pat<(Tail (iPTR texternalsym:$dst)),
            (PseudoTAIL texternalsym:$dst)>;

An extern function, for example, always matches the tglobaladdr pattern:

  def : Pat<(Tail (iPTR tglobaladdr:$dst)),
            (PseudoTAIL texternalsym:$dst)>;

And nothing ever seems to match the texternalsym pattern. I expected the following to match texternalsym since callee is an extern, but it matches tglobaladdr:

  declare void @callee()
  define void @CALLER2() {
    tail call void @callee()
    ret void
  }

I have addressed the rest of your comments and will push an updated version soon. Thanks.


https://reviews.llvm.org/D45395