[llvm] r332340 - [mips] Add disassembly support for comparison instructions
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Tue May 15 04:18:24 PDT 2018
Author: sdardis
Date: Tue May 15 04:18:24 2018
New Revision: 332340
URL: http://llvm.org/viewvc/llvm-project?rev=332340&view=rev
Log:
[mips] Add disassembly support for comparison instructions
Modified:
llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td
llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt
llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td?rev=332340&r1=332339&r2=332340&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td Tue May 15 04:18:24 2018
@@ -363,11 +363,13 @@ multiclass C_COND_MM<string TypeStr, Reg
let BaseOpcode = "c.ngt."#NAME;
}
}
+let DecoderNamespace = "MicroMips" in {
+ defm S : C_COND_MM<"s", FGR32Opnd, 0b00, II_C_CC_S>,
+ ISA_MICROMIPS32_NOT_MIPS32R6;
+ defm D32 : C_COND_MM<"d", AFGR64Opnd, 0b01, II_C_CC_D>,
+ ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
+}
-defm S : C_COND_MM<"s", FGR32Opnd, 0b00, II_C_CC_S>,
- ISA_MICROMIPS32_NOT_MIPS32R6;
-defm D32 : C_COND_MM<"d", AFGR64Opnd, 0b01, II_C_CC_D>,
- ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
let DecoderNamespace = "Mips64" in
defm D64 : C_COND_MM<"d", FGR64Opnd, 0b01, II_C_CC_D>,
ISA_MICROMIPS32_NOT_MIPS32R6, FGR_64;
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt?rev=332340&r1=332339&r2=332340&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt Tue May 15 04:18:24 2018
@@ -258,3 +258,35 @@
0x54 0x86 0x20 0x3b # CHECK: mfc1 $4, $f6
0x54 0x86 0x38 0x3b # CHECK: mthc1 $4, $f6
0x54 0x86 0x30 0x3b # CHECK: mfhc1 $4, $f6
+0x54 0xe6 0x00 0x3c # CHECK: c.f.s $f6, $f7
+0x54 0xe6 0x00 0x7c # CHECK: c.un.s $f6, $f7
+0x54 0xe6 0x00 0xbc # CHECK: c.eq.s $f6, $f7
+0x54 0xe6 0x01 0x3c # CHECK: c.olt.s $f6, $f7
+0x54 0xe6 0x01 0x7c # CHECK: c.ult.s $f6, $f7
+0x54 0xe6 0x01 0xbc # CHECK: c.ole.s $f6, $f7
+0x54 0xe6 0x01 0xfc # CHECK: c.ule.s $f6, $f7
+0x54 0xe6 0x02 0x3c # CHECK: c.sf.s $f6, $f7
+0x54 0xe6 0x02 0x7c # CHECK: c.ngle.s $f6, $f7
+0x54 0xe6 0x02 0xbc # CHECK: c.seq.s $f6, $f7
+0x54 0xe6 0x02 0xfc # CHECK: c.ngl.s $f6, $f7
+0x54 0xe6 0x03 0x3c # CHECK: c.lt.s $f6, $f7
+0x54 0xe6 0x03 0x7c # CHECK: c.nge.s $f6, $f7
+0x54 0xe6 0x03 0xbc # CHECK: c.le.s $f6, $f7
+0x54 0xe6 0x03 0xfc # CHECK: c.ngt.s $f6, $f7
+0x54 0x1e 0x06 0x3c # CHECK: c.sf.d $f30, $f0
+0x55 0xcc 0x04 0x3c # CHECK: c.f.d $f12, $f14
+0x55 0xcc 0x04 0x7c # CHECK: c.un.d $f12, $f14
+0x55 0xcc 0x04 0xbc # CHECK: c.eq.d $f12, $f14
+0x55 0xcc 0x04 0xfc # CHECK: c.ueq.d $f12, $f14
+0x55 0xcc 0x05 0x3c # CHECK: c.olt.d $f12, $f14
+0x55 0xcc 0x05 0x7c # CHECK: c.ult.d $f12, $f14
+0x55 0xcc 0x05 0xbc # CHECK: c.ole.d $f12, $f14
+0x55 0xcc 0x05 0xfc # CHECK: c.ule.d $f12, $f14
+0x55 0xcc 0x06 0x3c # CHECK: c.sf.d $f12, $f14
+0x55 0xcc 0x06 0x7c # CHECK: c.ngle.d $f12, $f14
+0x55 0xcc 0x06 0xbc # CHECK: c.seq.d $f12, $f14
+0x55 0xcc 0x06 0xfc # CHECK: c.ngl.d $f12, $f14
+0x55 0xcc 0x07 0x3c # CHECK: c.lt.d $f12, $f14
+0x55 0xcc 0x07 0x7c # CHECK: c.nge.d $f12, $f14
+0x55 0xcc 0x07 0xbc # CHECK: c.le.d $f12, $f14
+0x55 0xcc 0x07 0xfc # CHECK: c.ngt.d $f12, $f14
Modified: llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s?rev=332340&r1=332339&r2=332340&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s Tue May 15 04:18:24 2018
@@ -93,6 +93,70 @@
# CHECK-EL: nmadd.d $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x0a,0x11]
# CHECK-EL: nmsub.s $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x22,0x11]
# CHECK-EL: nmsub.d $f2, $f4, $f6, $f8 # encoding: [0x06,0x55,0x2a,0x11]
+# CHECK-EL: c.f.s $f6, $f7 # encoding: [0xe6,0x54,0x3c,0x00]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_F_S_MM
+# CHECK-EL: c.un.s $f6, $f7 # encoding: [0xe6,0x54,0x7c,0x00]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_UN_S_MM
+# CHECK-EL: c.eq.s $f6, $f7 # encoding: [0xe6,0x54,0xbc,0x00]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_EQ_S_MM
+# CHECK-EL: c.olt.s $f6, $f7 # encoding: [0xe6,0x54,0x3c,0x01]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_OLT_S_MM
+# CHECK-EL: c.ult.s $f6, $f7 # encoding: [0xe6,0x54,0x7c,0x01]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_ULT_S_MM
+# CHECK-EL: c.ole.s $f6, $f7 # encoding: [0xe6,0x54,0xbc,0x01]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_OLE_S_MM
+# CHECK-EL: c.ule.s $f6, $f7 # encoding: [0xe6,0x54,0xfc,0x01]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_ULE_S_MM
+# CHECK-EL: c.sf.s $f6, $f7 # encoding: [0xe6,0x54,0x3c,0x02]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_SF_S_MM
+# CHECK-EL: c.ngle.s $f6, $f7 # encoding: [0xe6,0x54,0x7c,0x02]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_NGLE_S_MM
+# CHECK-EL: c.seq.s $f6, $f7 # encoding: [0xe6,0x54,0xbc,0x02]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_SEQ_S_MM
+# CHECK-EL: c.ngl.s $f6, $f7 # encoding: [0xe6,0x54,0xfc,0x02]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_NGL_S_MM
+# CHECK-EL: c.lt.s $f6, $f7 # encoding: [0xe6,0x54,0x3c,0x03]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_LT_S_MM
+# CHECK-EL: c.nge.s $f6, $f7 # encoding: [0xe6,0x54,0x7c,0x03]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_NGE_S_MM
+# CHECK-EL: c.le.s $f6, $f7 # encoding: [0xe6,0x54,0xbc,0x03]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_LE_S_MM
+# CHECK-EL: c.ngt.s $f6, $f7 # encoding: [0xe6,0x54,0xfc,0x03]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_NGT_S_MM
+# CHECK-EL: c.sf.d $f30, $f0 # encoding: [0x1e,0x54,0x3c,0x06]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_SF_D32_MM
+# CHECK-EL: c.f.d $f12, $f14 # encoding: [0xcc,0x55,0x3c,0x04]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_F_D32_MM
+# CHECK-EL: c.un.d $f12, $f14 # encoding: [0xcc,0x55,0x7c,0x04]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_UN_D32_MM
+# CHECK-EL: c.eq.d $f12, $f14 # encoding: [0xcc,0x55,0xbc,0x04]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_EQ_D32_MM
+# CHECK-EL: c.ueq.d $f12, $f14 # encoding: [0xcc,0x55,0xfc,0x04]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_UEQ_D32_MM
+# CHECK-EL: c.olt.d $f12, $f14 # encoding: [0xcc,0x55,0x3c,0x05]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_OLT_D32_MM
+# CHECK-EL: c.ult.d $f12, $f14 # encoding: [0xcc,0x55,0x7c,0x05]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_ULT_D32_MM
+# CHECK-EL: c.ole.d $f12, $f14 # encoding: [0xcc,0x55,0xbc,0x05]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_OLE_D32_MM
+# CHECK-EL: c.ule.d $f12, $f14 # encoding: [0xcc,0x55,0xfc,0x05]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_ULE_D32_MM
+# CHECK-EL: c.sf.d $f12, $f14 # encoding: [0xcc,0x55,0x3c,0x06]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_SF_D32_MM
+# CHECK-EL: c.ngle.d $f12, $f14 # encoding: [0xcc,0x55,0x7c,0x06]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_NGLE_D32_MM
+# CHECK-EL: c.seq.d $f12, $f14 # encoding: [0xcc,0x55,0xbc,0x06]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_SEQ_D32_MM
+# CHECK-EL: c.ngl.d $f12, $f14 # encoding: [0xcc,0x55,0xfc,0x06]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_NGL_D32_MM
+# CHECK-EL: c.lt.d $f12, $f14 # encoding: [0xcc,0x55,0x3c,0x07]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_LT_D32_MM
+# CHECK-EL: c.nge.d $f12, $f14 # encoding: [0xcc,0x55,0x7c,0x07]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_NGE_D32_MM
+# CHECK-EL: c.le.d $f12, $f14 # encoding: [0xcc,0x55,0xbc,0x07]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_LE_D32_MM
+# CHECK-EL: c.ngt.d $f12, $f14 # encoding: [0xcc,0x55,0xfc,0x07]
+# CHECK-EL-NEXT: # <MCInst #{{[0-9]+}} C_NGT_D32_MM
#------------------------------------------------------------------------------
# Big endian
#------------------------------------------------------------------------------
@@ -187,6 +251,70 @@
# CHECK-EB: nmsub.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x22]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} NMSUB_S_MM
# CHECK-EB: nmsub.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x2a]
+# CHECK-EB: c.f.s $f6, $f7 # encoding: [0x54,0xe6,0x00,0x3c]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_F_S_MM
+# CHECK-EB: c.un.s $f6, $f7 # encoding: [0x54,0xe6,0x00,0x7c]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_UN_S_MM
+# CHECK-EB: c.eq.s $f6, $f7 # encoding: [0x54,0xe6,0x00,0xbc]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_EQ_S_MM
+# CHECK-EB: c.olt.s $f6, $f7 # encoding: [0x54,0xe6,0x01,0x3c]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_OLT_S_MM
+# CHECK-EB: c.ult.s $f6, $f7 # encoding: [0x54,0xe6,0x01,0x7c]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_ULT_S_MM
+# CHECK-EB: c.ole.s $f6, $f7 # encoding: [0x54,0xe6,0x01,0xbc]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_OLE_S_MM
+# CHECK-EB: c.ule.s $f6, $f7 # encoding: [0x54,0xe6,0x01,0xfc]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_ULE_S_MM
+# CHECK-EB: c.sf.s $f6, $f7 # encoding: [0x54,0xe6,0x02,0x3c]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_SF_S_MM
+# CHECK-EB: c.ngle.s $f6, $f7 # encoding: [0x54,0xe6,0x02,0x7c]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_NGLE_S_MM
+# CHECK-EB: c.seq.s $f6, $f7 # encoding: [0x54,0xe6,0x02,0xbc]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_SEQ_S_MM
+# CHECK-EB: c.ngl.s $f6, $f7 # encoding: [0x54,0xe6,0x02,0xfc]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_NGL_S_MM
+# CHECK-EB: c.lt.s $f6, $f7 # encoding: [0x54,0xe6,0x03,0x3c]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_LT_S_MM
+# CHECK-EB: c.nge.s $f6, $f7 # encoding: [0x54,0xe6,0x03,0x7c]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_NGE_S_MM
+# CHECK-EB: c.le.s $f6, $f7 # encoding: [0x54,0xe6,0x03,0xbc]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_LE_S_MM
+# CHECK-EB: c.ngt.s $f6, $f7 # encoding: [0x54,0xe6,0x03,0xfc]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_NGT_S_MM
+# CHECK-EB: c.sf.d $f30, $f0 # encoding: [0x54,0x1e,0x06,0x3c]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_SF_D32_MM
+# CHECK-EB: c.f.d $f12, $f14 # encoding: [0x55,0xcc,0x04,0x3c]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_F_D32_MM
+# CHECK-EB: c.un.d $f12, $f14 # encoding: [0x55,0xcc,0x04,0x7c]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_UN_D32_MM
+# CHECK-EB: c.eq.d $f12, $f14 # encoding: [0x55,0xcc,0x04,0xbc]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_EQ_D32_MM
+# CHECK-EB: c.ueq.d $f12, $f14 # encoding: [0x55,0xcc,0x04,0xfc]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_UEQ_D32_MM
+# CHECK-EB: c.olt.d $f12, $f14 # encoding: [0x55,0xcc,0x05,0x3c]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_OLT_D32_MM
+# CHECK-EB: c.ult.d $f12, $f14 # encoding: [0x55,0xcc,0x05,0x7c]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_ULT_D32_MM
+# CHECK-EB: c.ole.d $f12, $f14 # encoding: [0x55,0xcc,0x05,0xbc]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_OLE_D32_MM
+# CHECK-EB: c.ule.d $f12, $f14 # encoding: [0x55,0xcc,0x05,0xfc]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_ULE_D32_MM
+# CHECK-EB: c.sf.d $f12, $f14 # encoding: [0x55,0xcc,0x06,0x3c]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_SF_D32_MM
+# CHECK-EB: c.ngle.d $f12, $f14 # encoding: [0x55,0xcc,0x06,0x7c]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_NGLE_D32_MM
+# CHECK-EB: c.seq.d $f12, $f14 # encoding: [0x55,0xcc,0x06,0xbc]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_SEQ_D32_MM
+# CHECK-EB: c.ngl.d $f12, $f14 # encoding: [0x55,0xcc,0x06,0xfc]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_NGL_D32_MM
+# CHECK-EB: c.lt.d $f12, $f14 # encoding: [0x55,0xcc,0x07,0x3c]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_LT_D32_MM
+# CHECK-EB: c.nge.d $f12, $f14 # encoding: [0x55,0xcc,0x07,0x7c]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_NGE_D32_MM
+# CHECK-EB: c.le.d $f12, $f14 # encoding: [0x55,0xcc,0x07,0xbc]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_LE_D32_MM
+# CHECK-EB: c.ngt.d $f12, $f14 # encoding: [0x55,0xcc,0x07,0xfc]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} C_NGT_D32_MM
add.s $f4, $f6, $f8
add.d $f4, $f6, $f8
@@ -246,3 +374,35 @@
nmadd.d $f2, $f4, $f6, $f8
nmsub.s $f2, $f4, $f6, $f8
nmsub.d $f2, $f4, $f6, $f8
+ c.f.s $f6, $f7
+ c.un.s $f6, $f7
+ c.eq.s $f6, $f7
+ c.olt.s $f6, $f7
+ c.ult.s $f6, $f7
+ c.ole.s $f6, $f7
+ c.ule.s $f6, $f7
+ c.sf.s $f6, $f7
+ c.ngle.s $f6, $f7
+ c.seq.s $f6, $f7
+ c.ngl.s $f6, $f7
+ c.lt.s $f6, $f7
+ c.nge.s $f6, $f7
+ c.le.s $f6, $f7
+ c.ngt.s $f6, $f7
+ c.sf.d $f30, $f0
+ c.f.d $f12, $f14
+ c.un.d $f12, $f14
+ c.eq.d $f12, $f14
+ c.ueq.d $f12, $f14
+ c.olt.d $f12, $f14
+ c.ult.d $f12, $f14
+ c.ole.d $f12, $f14
+ c.ule.d $f12, $f14
+ c.sf.d $f12, $f14
+ c.ngle.d $f12, $f14
+ c.seq.d $f12, $f14
+ c.ngl.d $f12, $f14
+ c.lt.d $f12, $f14
+ c.nge.d $f12, $f14
+ c.le.d $f12, $f14
+ c.ngt.d $f12, $f14
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