[llvm] r332301 - [AArch64] enhance test to show FMF loss; NFC

[Sanjay Patel via llvm-commits]

Author: spatel
Date: Mon May 14 14:53:21 2018
New Revision: 332301

URL: http://llvm.org/viewvc/llvm-project?rev=332301&view=rev
Log:
[AArch64] enhance test to show FMF loss; NFC

Modified:
    llvm/trunk/test/CodeGen/AArch64/vecreduce-propagate-sd-flags.ll

Modified: llvm/trunk/test/CodeGen/AArch64/vecreduce-propagate-sd-flags.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/vecreduce-propagate-sd-flags.ll?rev=332301&r1=332300&r2=332301&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/vecreduce-propagate-sd-flags.ll (original)
+++ llvm/trunk/test/CodeGen/AArch64/vecreduce-propagate-sd-flags.ll Mon May 14 14:53:21 2018
@@ -9,6 +9,7 @@
 ; CHECK-NEXT: Analyzing result type: v4f64
 ; CHECK-NEXT: Split node result: [[VFOUR]]: v4f64 = BUILD_VECTOR
 
+; FIXME: We dropped the 'reassoc' flag.
 ; CHECK: Legalizing node: [[VTWO:t.*]]: v2f64 = BUILD_VECTOR
 ; CHECK: Legally typed node: [[VTWO]]: v2f64 = BUILD_VECTOR
 ; CHECK: Legalizing node: t26: v2f64 = fmaxnum nnan [[VTWO]], [[VTWO]]
@@ -24,7 +25,7 @@ entry:
  %1 = insertelement <4 x double> %0, double 1.0, i32 1
  %2 = insertelement <4 x double> %1, double 1.0, i32 2
  %3 = insertelement <4 x double> %2, double 1.0, i32 3
- %4 = call nnan double @llvm.experimental.vector.reduce.fmax.f64.v4f64(<4 x double> %3)
+ %4 = call nnan reassoc double @llvm.experimental.vector.reduce.fmax.f64.v4f64(<4 x double> %3)
  ret double %4
 }