[PATCH] D46837: [MachineScheduler] Skip an implicit def of a super-reg added by regalloc in findDefIdx.

[Jonas Paulsson via Phabricator via llvm-commits]

jonpa created this revision.
jonpa added reviewers: atrick, fhahn.

When working with the scheduler in regards to SystemZ WriteLatencys, I came across cases where the mapping from SchedWrite entry to MI def operands (mapped by the ordering) were corrupted by implicit def operands added by regalloc. The specific register was "CC", which is an implicitly defined register part of the MCInstrDesc.

Since regalloc will not put its implicit-def operands last in list, I believe the right fix is to ignore those when carefully looking up the def index in findDefIdx.

If approved, I will hopefully commit this soon with SystemZ SchedModel improvements.


https://reviews.llvm.org/D46837

Files:
  lib/CodeGen/TargetSchedule.cpp


Index: lib/CodeGen/TargetSchedule.cpp
===================================================================
--- lib/CodeGen/TargetSchedule.cpp
+++ lib/CodeGen/TargetSchedule.cpp
@@ -154,12 +154,15 @@
 /// is independent of use operands. Def operands may be reordered with uses or
 /// merged with uses without affecting the def index (e.g. before/after
 /// regalloc). However, an instruction's def operands must never be reordered
-/// with respect to each other.
+/// with respect to each other.  We need to skip implicit def operands (added
+/// by regalloc) that are not part of the MCInstrDesc.
 static unsigned findDefIdx(const MachineInstr *MI, unsigned DefOperIdx) {
+  const MCInstrDesc &MID = MI->getDesc();
   unsigned DefIdx = 0;
   for (unsigned i = 0; i != DefOperIdx; ++i) {
     const MachineOperand &MO = MI->getOperand(i);
-    if (MO.isReg() && MO.isDef())
+    if (MO.isReg() && MO.isDef() &&
+        (!MO.isImplicit() || MID.hasImplicitDefOfPhysReg(MO.getReg())))
       ++DefIdx;
   }
   return DefIdx;


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D46837.146638.patch
Type: text/x-patch
Size: 1024 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20180514/5114f917/attachment.bin>