[llvm] r332097 - [mips] Enable disassembly of fused (negative) multiply add/sub instructions
Simon Dardis via llvm-commits
llvm-commits at lists.llvm.org
Fri May 11 08:21:40 PDT 2018
Author: sdardis
Date: Fri May 11 08:21:40 2018
New Revision: 332097
URL: http://llvm.org/viewvc/llvm-project?rev=332097&view=rev
Log:
[mips] Enable disassembly of fused (negative) multiply add/sub instructions
Reviewers: atanasyan, smaksimovic, abeserminji
Differential Revision: https://reviews.llvm.org/D46392
Modified:
llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td
llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt
llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s
Modified: llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td?rev=332097&r1=332096&r2=332097&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MicroMipsInstrFPU.td Fri May 11 08:21:40 2018
@@ -197,24 +197,31 @@ def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR
def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,
II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>,
ISA_MICROMIPS;
+}
-def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
- MADDS_FM_MM<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6;
-def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
- MADDS_FM_MM<0x21>, ISA_MICROMIPS32_NOT_MIPS32R6;
-def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
- MADDS_FM_MM<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6;
-def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
- MADDS_FM_MM<0x22>, ISA_MICROMIPS32_NOT_MIPS32R6;
-
-def MADD_D32_MM : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
- MADDS_FM_MM<0x9>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
-def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
- MADDS_FM_MM<0x29>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
-def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
- MADDS_FM_MM<0xa>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
-def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
- MADDS_FM_MM<0x2a>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
+let DecoderNamespace = "MicroMips" in {
+ def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S>,
+ MADDS_FM_MM<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6, MADD4;
+ def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S>,
+ MADDS_FM_MM<0x21>, ISA_MICROMIPS32_NOT_MIPS32R6, MADD4;
+ let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {
+ def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S>,
+ MADDS_FM_MM<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6;
+ def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S>,
+ MADDS_FM_MM<0x22>, ISA_MICROMIPS32_NOT_MIPS32R6;
+ }
+ def MADD_D32_MM : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D>,
+ MADDS_FM_MM<0x9>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32,
+ MADD4;
+ def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D>,
+ MADDS_FM_MM<0x29>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32,
+ MADD4;
+ let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {
+ def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D>,
+ MADDS_FM_MM<0xa>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
+ def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D>,
+ MADDS_FM_MM<0x2a>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
+ }
}
def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd,
Modified: llvm/trunk/lib/Target/Mips/MipsInstrFPU.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsInstrFPU.td?rev=332097&r1=332096&r2=332097&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsInstrFPU.td (original)
+++ llvm/trunk/lib/Target/Mips/MipsInstrFPU.td Fri May 11 08:21:40 2018
@@ -606,38 +606,39 @@ let AdditionalPredicates = [NotInMicroMi
defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>;
}
-def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
- MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4;
-def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
- MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4;
+let AdditionalPredicates = [NotInMicroMips, HasMadd4] in {
+ def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
+ MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
+ def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
+ MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
+}
-let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {
+let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in {
def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
MADDS_FM<7, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
}
-
-def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
- MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32, MADD4;
-def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
- MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32, MADD4;
-
-let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {
+let AdditionalPredicates = [NotInMicroMips, HasMadd4] in {
+ def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
+ MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
+ def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
+ MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
+}
+let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in {
def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
}
-
-let DecoderNamespace = "MipsFP64" in {
- def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
- MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64, MADD4;
- def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
- MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64, MADD4;
+let AdditionalPredicates = [NotInMicroMips, HasMadd4, NotInMicroMips],
+ DecoderNamespace = "MipsFP64" in {
+ def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
+ MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
+ def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
+ MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
}
-
-let AdditionalPredicates = [NoNaNsFPMath, HasMadd4],
+let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips],
DecoderNamespace = "MipsFP64" in {
def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt?rev=332097&r1=332096&r2=332097&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt Fri May 11 08:21:40 2018
@@ -234,3 +234,11 @@
0x02 0x54 0x7b 0x1b # CHECK: cvt.s.d $f0, $f2
0x07 0x00 0x7c 0x6b # CHECK: sync 7
0x03 0x42 0x00 0x04 # CHECK: synci 1024($3)
+0xc4 0x54 0x81 0x00 # CHECK: madd.s $f0, $f2, $f4, $f6
+0xc4 0x54 0x89 0x00 # CHECK: madd.d $f0, $f2, $f4, $f6
+0xc4 0x54 0x82 0x00 # CHECK: nmadd.s $f0, $f2, $f4, $f6
+0xc4 0x54 0x8a 0x00 # CHECK: nmadd.d $f0, $f2, $f4, $f6
+0xc4 0x54 0xa1 0x00 # CHECK: msub.s $f0, $f2, $f4, $f6
+0xc4 0x54 0xa9 0x00 # CHECK: msub.d $f0, $f2, $f4, $f6
+0xc4 0x54 0xa2 0x00 # CHECK: nmsub.s $f0, $f2, $f4, $f6
+0xc4 0x54 0xaa 0x00 # CHECK: nmsub.d $f0, $f2, $f4, $f6
Modified: llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt?rev=332097&r1=332096&r2=332097&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt (original)
+++ llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt Fri May 11 08:21:40 2018
@@ -236,3 +236,11 @@
0x54 0x02 0x13 0x7b # CHECK: cvt.d.s $f0, $f2
0x54 0x02 0x33 0x7b # CHECK: cvt.d.w $f0, $f2
0x54 0x02 0x1b 0x7b # CHECK: cvt.s.d $f0, $f2
+0x54 0xc4 0x00 0x81 # CHECK: madd.s $f0, $f2, $f4, $f6
+0x54 0xc4 0x00 0x89 # CHECK: madd.d $f0, $f2, $f4, $f6
+0x54 0xc4 0x00 0x82 # CHECK: nmadd.s $f0, $f2, $f4, $f6
+0x54 0xc4 0x00 0x8a # CHECK: nmadd.d $f0, $f2, $f4, $f6
+0x54 0xc4 0x00 0xa1 # CHECK: msub.s $f0, $f2, $f4, $f6
+0x54 0xc4 0x00 0xa9 # CHECK: msub.d $f0, $f2, $f4, $f6
+0x54 0xc4 0x00 0xa2 # CHECK: nmsub.s $f0, $f2, $f4, $f6
+0x54 0xc4 0x00 0xaa # CHECK: nmsub.d $f0, $f2, $f4, $f6
Modified: llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s?rev=332097&r1=332096&r2=332097&view=diff
==============================================================================
--- llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s (original)
+++ llvm/trunk/test/MC/Mips/micromips-fpu-instructions.s Fri May 11 08:21:40 2018
@@ -153,12 +153,19 @@
# CHECK-EB: movf.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x20]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVF_D32_MM
# CHECK-EB: madd.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x01]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MADD_S_MM
# CHECK-EB: madd.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x09]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MADD_D32_MM
# CHECK-EB: msub.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x21]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MSUB_S_MM
# CHECK-EB: msub.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x29]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MSUB_D32_MM
# CHECK-EB: nmadd.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x02]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} NMADD_S_MM
# CHECK-EB: nmadd.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x0a]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} NMADD_D32_MM
# CHECK-EB: nmsub.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x22]
+# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} NMSUB_S_MM
# CHECK-EB: nmsub.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x2a]
add.s $f4, $f6, $f8
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