[PATCH] D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes.

[Javed Absar via Phabricator via llvm-commits]

javed.absar added inline comments.


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Comment at: include/llvm/Target/TargetInstrPredicate.td:48
+
+// Check if operands at indices `First` and `Second` are the same register.
+class CheckSameRegOperand<int First, int Second> : MCPredicate {
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Where is the check itself? Maybe the comment is not right or I am not getting this right.


https://reviews.llvm.org/D46695